Commit cd83b258 authored by Tom Levens's avatar Tom Levens

Propagate defaults to parameters on vme64x_core

Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 0ae24a25
...@@ -12,46 +12,46 @@ use work.vme64x_pkg.all; ...@@ -12,46 +12,46 @@ use work.vme64x_pkg.all;
entity vme64x_core is entity vme64x_core is
generic ( generic (
g_clock_period : natural; g_clock_period : natural;
g_decode_am : boolean; g_decode_am : boolean := true;
g_user_csr_ext : boolean; g_user_csr_ext : boolean := false;
g_wb_granularity : t_wishbone_address_granularity; g_wb_granularity : t_wishbone_address_granularity;
g_manufacturer_id : std_logic_vector(23 downto 0); g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0); g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0); g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0); g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0); g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0); g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0); g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0); g_beg_cram : std_logic_vector(23 downto 0) := x"000000";
g_end_cram : std_logic_vector(23 downto 0); g_end_cram : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_csr : std_logic_vector(23 downto 0); g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0); g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0); g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0); g_end_sn : std_logic_vector(23 downto 0) := x"000000";
g_decoder_0_adem : std_logic_vector(31 downto 0); g_decoder_0_adem : std_logic_vector(31 downto 0) := x"ff000000";
g_decoder_0_amcap : std_logic_vector(63 downto 0); g_decoder_0_amcap : std_logic_vector(63 downto 0) := x"00000000_0000ff00";
g_decoder_0_dawpr : std_logic_vector(7 downto 0); g_decoder_0_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_1_adem : std_logic_vector(31 downto 0); g_decoder_1_adem : std_logic_vector(31 downto 0) := x"fff80000";
g_decoder_1_amcap : std_logic_vector(63 downto 0); g_decoder_1_amcap : std_logic_vector(63 downto 0) := x"ff000000_00000000";
g_decoder_1_dawpr : std_logic_vector(7 downto 0); g_decoder_1_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_2_adem : std_logic_vector(31 downto 0); g_decoder_2_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_2_amcap : std_logic_vector(63 downto 0); g_decoder_2_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_2_dawpr : std_logic_vector(7 downto 0); g_decoder_2_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_3_adem : std_logic_vector(31 downto 0); g_decoder_3_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_3_amcap : std_logic_vector(63 downto 0); g_decoder_3_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_3_dawpr : std_logic_vector(7 downto 0); g_decoder_3_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_4_adem : std_logic_vector(31 downto 0); g_decoder_4_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_4_amcap : std_logic_vector(63 downto 0); g_decoder_4_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_4_dawpr : std_logic_vector(7 downto 0); g_decoder_4_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_5_adem : std_logic_vector(31 downto 0); g_decoder_5_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_5_amcap : std_logic_vector(63 downto 0); g_decoder_5_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_5_dawpr : std_logic_vector(7 downto 0); g_decoder_5_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_6_adem : std_logic_vector(31 downto 0); g_decoder_6_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_6_amcap : std_logic_vector(63 downto 0); g_decoder_6_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_6_dawpr : std_logic_vector(7 downto 0); g_decoder_6_dawpr : std_logic_vector(7 downto 0) := x"84";
g_decoder_7_adem : std_logic_vector(31 downto 0); g_decoder_7_adem : std_logic_vector(31 downto 0) := x"00000000";
g_decoder_7_amcap : std_logic_vector(63 downto 0); g_decoder_7_amcap : std_logic_vector(63 downto 0) := x"00000000_00000000";
g_decoder_7_dawpr : std_logic_vector(7 downto 0)); g_decoder_7_dawpr : std_logic_vector(7 downto 0) := x"84");
port ( port (
clk_i : std_logic; clk_i : std_logic;
rst_n_i : std_logic; rst_n_i : std_logic;
...@@ -92,16 +92,16 @@ entity vme64x_core is ...@@ -92,16 +92,16 @@ entity vme64x_core is
wb_sel_o : out t_wishbone_byte_select; wb_sel_o : out t_wishbone_byte_select;
wb_we_o : out std_logic; wb_we_o : out std_logic;
wb_dat_o : out t_wishbone_data; wb_dat_o : out t_wishbone_data;
int_i : std_logic; int_i : std_logic := '0';
irq_ack_o : out std_logic; irq_ack_o : out std_logic;
irq_level_i : std_logic_vector(2 downto 0); irq_level_i : std_logic_vector(2 downto 0) := (others => '0');
irq_vector_i : std_logic_vector(7 downto 0); irq_vector_i : std_logic_vector(7 downto 0) := (others => '0');
user_csr_addr_o : out std_logic_vector(18 downto 2); user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : std_logic_vector(7 downto 0); user_csr_data_i : std_logic_vector(7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector(7 downto 0); user_csr_data_o : out std_logic_vector(7 downto 0);
user_csr_we_o : out std_logic; user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2); user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : std_logic_vector(7 downto 0)); user_cr_data_i : std_logic_vector(7 downto 0) := (others => '0'));
end vme64x_core; end vme64x_core;
architecture unwrap of vme64x_core is architecture unwrap of vme64x_core is
......
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