xvme64x_core is now the top-level entity, vme64x_core is a wrapper.

d1f969c8 · Tristan Gingold · 22994dc6 · d1f969c8 · d1f969c8 · d1f969c8
Commit d1f969c8 authored Nov 24, 2017 by Tristan Gingold
5 changed files
--- a/hdl/rtl/vme64x_core.vhd
+++ b/hdl/rtl/vme64x_core.vhd
--- a/hdl/rtl/vme64x_pkg.vhd
+++ b/hdl/rtl/vme64x_pkg.vhd
--- a/hdl/rtl/vme_bus.vhd
+++ b/hdl/rtl/vme_bus.vhd
@@ -69,9 +69,7 @@ use work.vme64x_pkg.all;
 entity vme_bus is
  generic (
-    g_CLOCK_PERIOD  : integer;
+    g_CLOCK_PERIOD  : integer
-    g_WB_DATA_WIDTH : integer;
-    g_WB_ADDR_WIDTH : integer
  );
  port (
    clk_i           : in  std_logic;
@@ -104,9 +102,9 @@ entity vme_bus is
    -- WB signals
    stb_o           : out std_logic;
    ack_i           : in  std_logic;
-    dat_o           : out std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
+    dat_o           : out std_logic_vector(31 downto 0);
-    dat_i           : in  std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
+    dat_i           : in  std_logic_vector(31 downto 0);
-    adr_o           : out std_logic_vector(g_WB_ADDR_WIDTH-1 downto 0);
+    adr_o           : out std_logic_vector(31 downto 0);
    sel_o           : out std_logic_vector(3 downto 0);
    we_o            : out std_logic;
    cyc_o           : out std_logic;
@@ -241,10 +239,6 @@ architecture rtl of vme_bus is
  signal s_DS_latch_count           : unsigned (2 downto 0);
 begin
-  --  Consistency check.
-  assert g_WB_DATA_WIDTH = 32 report "g_WB_DATA_WIDTH must be set to 32"
-    severity failure;
  -- These output signals are connected to the buffers on the board
  -- SN74VMEH22501A Function table:  (A is fpga, B is VME connector)
  --   OEn | DIR | OUTPUT                 OEAB   |   OEBYn   |   OUTPUT

--- a/hdl/rtl/xvme64x_core.vhd
+++ b/hdl/rtl/xvme64x_core.vhd
--- a/hdl/testbench/simple_tb/top_tb.vhd
+++ b/hdl/testbench/simple_tb/top_tb.vhd