Commit de63753d authored by Tom Levens's avatar Tom Levens

Cleanup

Move user CR/CSR space to VME64xCore_Top with generic to enable/disable
it. Standardise generic default values between VME64xCore_Top and
xvme64x_core.
Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 6a0fe9f8
......@@ -111,20 +111,21 @@ use work.vme64x_pack.all;
entity VME64xCore_Top is
generic (
g_clock : integer := c_clk_period; -- Clock period (ns)
g_wb_data_width : integer := c_width; -- WB data width: must be 32 or 64
g_wb_addr_width : integer := c_addr_width; -- WB address width: 64 or less
g_clock : integer := c_clk_period; -- Clock period (ns)
g_wb_data_width : integer := c_width; -- WB data width: must be 32 or 64
g_wb_addr_width : integer := c_addr_width; -- WB address width: 64 or less
g_user_csr_ext : boolean := false; -- Use external user CSR
-- Manufacturer ID: IEEE OUID
-- e.g. CERN is 0x080030
g_manufacturer_id : std_logic_vector(23 downto 0) := x"000000";
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
-- Board ID: Per manufacturer, each board shall have an unique ID
-- e.g. SVEC = 408 (CERN IDs: http://cern.ch/boardid)
g_board_id : std_logic_vector(31 downto 0) := x"00000000";
g_board_id : std_logic_vector(31 downto 0) := c_svec_id;
-- Revision ID: user defined revision code
g_revision_id : std_logic_vector(31 downto 0) := x"00000000";
g_revision_id : std_logic_vector(31 downto 0) := c_revision_id;
-- Program ID: Defined per AV1:
-- 0x00 = Not used
......@@ -134,7 +135,7 @@ entity VME64xCore_Top is
-- 0x80-0xEF = Reserved for future use
-- 0xF0-0xFE = Reserved for Boot Firmware (P1275)
-- 0xFF = Not to be used
g_program_id : std_logic_vector(7 downto 0) := x"00";
g_program_id : std_logic_vector(7 downto 0) := c_program_id;
-- Pointer to a user defined ASCII string
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
......@@ -143,11 +144,11 @@ entity VME64xCore_Top is
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"000000";
g_end_cram : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001003";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_csr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
......@@ -159,8 +160,8 @@ entity VME64xCore_Top is
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
-- Function 1
g_f1_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f1_adem : std_logic_vector( 31 downto 0) := x"fff80000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
......@@ -251,18 +252,22 @@ entity VME64xCore_Top is
WE_o : out std_logic;
STALL_i : in std_logic;
-- For the swapper
endian_i : in std_logic_vector(2 downto 0) := (others => '0');
-- User CR/CSR
-- User CSR
-- The following signals are used when g_user_csr_ext = true
-- otherwise they are connected to the internal user CSR.
endian_i : in std_logic_vector( 2 downto 0) := (others => '0');
irq_level_i : in std_logic_vector( 7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
-- User CR
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
-- Functions
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
......@@ -286,13 +291,10 @@ entity VME64xCore_Top is
-- Interrupt cycle it sends a pulse to the
-- IRQ Generator
irq_i : in std_logic; -- Interrupt request; the IRQ Generator/your
irq_i : in std_logic -- Interrupt request; the IRQ Generator/your
-- Wb application sends a pulse to the IRQ
-- Controller which asserts one of the IRQ
-- lines.
irq_level_i : in std_logic_vector(7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector(7 downto 0) := (others => '0')
);
end VME64xCore_Top;
......@@ -329,9 +331,17 @@ architecture RTL of VME64xCore_Top is
signal s_f7_ader : std_logic_vector(31 downto 0);
signal s_module_reset : std_logic;
signal s_module_enable : std_logic;
signal s_bar : std_logic_vector(4 downto 0);
signal s_bar : std_logic_vector( 4 downto 0);
signal s_vme_berr_n : std_logic;
signal s_irq_vector : std_logic_vector( 7 downto 0);
signal s_irq_level : std_logic_vector( 7 downto 0);
signal s_endian : std_logic_vector( 2 downto 0);
signal s_user_csr_addr : std_logic_vector(18 downto 2);
signal s_user_csr_data_i : std_logic_vector( 7 downto 0);
signal s_user_csr_data_o : std_logic_vector( 7 downto 0);
signal s_user_csr_we : std_logic;
-- Oversampled input signals
signal s_VME_RST_n : std_logic_vector(2 downto 0);
signal s_VME_AS_n : std_logic_vector(2 downto 0);
......@@ -453,7 +463,7 @@ begin
f5_ader_i => s_f5_ader,
f6_ader_i => s_f6_ader,
f7_ader_i => s_f7_ader,
endian_i => endian_i,
endian_i => s_endian,
module_enable_i => s_module_enable,
bar_i => s_bar
);
......@@ -503,8 +513,8 @@ begin
VME_AS_n_i => s_VME_AS_n(2),
VME_DS_n_i => s_VME_DS_n(5 downto 4),
VME_ADDR_123_i => VME_ADDR_i(3 downto 1),
INT_Level_i => irq_level_i,
INT_Vector_i => irq_vector_i,
INT_Level_i => s_irq_level,
INT_Vector_i => s_irq_vector,
INT_Req_i => irq_i,
VME_IRQ_n_o => s_VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
......@@ -582,10 +592,10 @@ begin
data_o => s_cr_csr_data_o,
we_i => s_cr_csr_we,
user_csr_addr_o => user_csr_addr_o,
user_csr_data_i => user_csr_data_i,
user_csr_data_o => user_csr_data_o,
user_csr_we_o => user_csr_we_o,
user_csr_addr_o => s_user_csr_addr,
user_csr_data_i => s_user_csr_data_i,
user_csr_data_o => s_user_csr_data_o,
user_csr_we_o => s_user_csr_we,
user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => user_cr_data_i,
......@@ -618,4 +628,35 @@ begin
f7_dfs_adem_i => f7_dfs_adem_i
);
-- User CSR space
gen_int_user_csr : if g_user_csr_ext = false generate
Inst_VME_User_CSR : VME_User_CSR
generic map (
g_wb_data_width => g_wb_data_width
)
port map (
clk_i => clk_i,
rst_n_i => s_reset_n,
addr_i => s_user_csr_addr,
data_i => s_user_csr_data_o,
data_o => s_user_csr_data_i,
we_i => s_user_csr_we,
irq_vector_o => s_irq_vector,
irq_level_o => s_irq_level,
endian_o => s_endian,
time_i => x"0000000000",
bytes_i => x"0000"
);
end generate;
gen_ext_user_csr : if g_user_csr_ext = true generate
s_user_csr_data_i <= user_csr_data_i;
s_endian <= endian_i;
s_irq_vector <= irq_vector_i;
s_irq_level <= irq_level_i;
end generate;
user_csr_addr_o <= s_user_csr_addr;
user_csr_data_o <= s_user_csr_data_o;
user_csr_we_o <= s_user_csr_we;
end RTL;
......@@ -233,14 +233,15 @@ architecture rtl of VME_CR_CSR_Space is
signal s_reg_cram_owner : std_logic_vector(7 downto 0);
signal s_reg_usr_bit_reg : std_logic_vector(7 downto 0);
type t_reg_array is array (0 to 7) of std_logic_vector(31 downto 0);
type t_reg_array is array (integer range <>) of std_logic_vector(31 downto 0);
signal s_reg_ader : t_reg_array;
signal s_ader : t_reg_array;
signal s_faf_ader : t_reg_array;
signal s_dfs_adem : t_reg_array;
signal s_reg_ader : t_reg_array(0 to 7);
signal s_ader : t_reg_array(0 to 7);
signal s_faf_ader : t_reg_array(0 to 7);
signal s_dfs_adem : t_reg_array(0 to 7);
constant c_adem : t_reg_array := (
constant c_adem : t_reg_array(-1 to 7) := (
x"00000000",
g_f0_adem, g_f1_adem, g_f2_adem, g_f3_adem,
g_f4_adem, g_f5_adem, g_f6_adem, g_f7_adem
);
......@@ -411,17 +412,7 @@ begin
process (s_reg_ader, s_faf_ader, s_dfs_adem)
begin
-- Function 0
if c_adem(0)(ADEM_FAF) = '1' then
s_ader(0) <= s_faf_ader(0);
elsif c_adem(0)(ADEM_DFS) = '1' and s_reg_ader(0)(ADER_DFSR) = '1' then
s_ader(0) <= s_dfs_adem(0)(31 downto 8) & s_reg_ader(0)(7 downto 0);
else
s_ader(0) <= s_reg_ader(0);
end if;
-- Function 1..7
for i in 1 to 7 loop
for i in 0 to 7 loop
if (c_adem(i-1)(ADEM_EFM) = '1' and c_adem(i-1)(ADEM_FAF) = '1') or
(c_adem(i-1)(ADEM_EFM) = '0' and c_adem(i)(ADEM_FAF) = '1')
then
......
......@@ -340,54 +340,55 @@ package vme64x_pack is
component VME64xCore_Top
generic (
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0);
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_beg_sn : std_logic_vector(23 downto 0);
g_end_sn : std_logic_vector(23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f0_dawpr : std_logic_vector( 7 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f1_dawpr : std_logic_vector( 7 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f2_dawpr : std_logic_vector( 7 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f3_dawpr : std_logic_vector( 7 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f4_dawpr : std_logic_vector( 7 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f5_dawpr : std_logic_vector( 7 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f6_dawpr : std_logic_vector( 7 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0);
g_f7_dawpr : std_logic_vector( 7 downto 0)
g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_user_csr_ext : boolean := false;
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
g_board_id : std_logic_vector(31 downto 0) := c_svec_id;
g_revision_id : std_logic_vector(31 downto 0) := c_revision_id;
g_program_id : std_logic_vector(7 downto 0) := c_program_id;
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001003";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f1_adem : std_logic_vector( 31 downto 0) := x"fff80000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f7_dawpr : std_logic_vector( 7 downto 0) := x"84"
);
port (
clk_i : in std_logic;
......@@ -430,6 +431,8 @@ package vme64x_pack is
WE_o : out std_logic;
STALL_i : in std_logic;
endian_i : in std_logic_vector( 2 downto 0) := (others => '0');
irq_level_i : in std_logic_vector( 7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
......@@ -453,9 +456,7 @@ package vme64x_pack is
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
irq_ack_o : out std_logic;
irq_i : in std_logic;
irq_level_i : in std_logic_vector(7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector(7 downto 0) := (others => '0')
irq_i : in std_logic
);
end component;
......@@ -917,6 +918,7 @@ package body vme64x_pack is
cr(16#001#) := x"00"; -- Length of CR (excluding CRC)
cr(16#002#) := x"03";
cr(16#003#) := x"ff";
cr(16#004#) := x"81"; -- CR data access width
cr(16#005#) := x"81"; -- CSR data access width
cr(16#006#) := x"02"; -- CR/CSR Space Specification ID
......@@ -975,6 +977,11 @@ package body vme64x_pack is
cr(16#036#) := end_sn(15 downto 8);
cr(16#037#) := end_sn( 7 downto 0);
cr(16#038#) := x"04"; -- Slave characteristics parameter
cr(16#039#) := x"00"; -- User-defined slave characteristics parameter
cr(16#03D#) := x"0E"; -- Interrupter capabilities
cr(16#03F#) := x"81"; -- CRAM data access width
cr(16#040#) := f0_dawpr;
......
......@@ -139,6 +139,10 @@ entity xvme64x_core is
irq_i : in std_logic;
irq_ack_o : out std_logic;
irq_level_i : in std_logic_vector( 7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector( 7 downto 0) := (others => '0');
endian_i : in std_logic_vector( 2 downto 0) := (others => '0');
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
......@@ -173,13 +177,6 @@ architecture wrapper of xvme64x_core is
signal dat_out,
dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(31 downto 0);
signal irq_vector,
irq_level : std_logic_vector( 7 downto 0);
signal endian : std_logic_vector( 2 downto 0);
signal user_csr_addr : std_logic_vector(18 downto 2);
signal user_csr_data_in,
user_csr_data_out : std_logic_vector( 7 downto 0);
signal user_csr_we : std_logic;
begin -- wrapper
......@@ -277,19 +274,19 @@ begin -- wrapper
WE_o => master_o.we,
STALL_i => master_i.stall,
endian_i => endian,
endian_i => endian_i,
user_csr_addr_o => user_csr_addr,
user_csr_data_i => user_csr_data_in,
user_csr_data_o => user_csr_data_out,
user_csr_we_o => user_csr_we,
user_csr_addr_o => user_csr_addr_o,
user_csr_data_i => user_csr_data_i,
user_csr_data_o => user_csr_data_o,
user_csr_we_o => user_csr_we_o,
user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => user_cr_data_i,
irq_i => irq_i,
irq_ack_o => irq_ack_o,
irq_vector_i => irq_vector,
irq_level_i => irq_level,
irq_vector_i => irq_vector_i,
irq_level_i => irq_level_i,
f0_faf_ader_i => f0_faf_ader_i,
f1_faf_ader_i => f1_faf_ader_i,
......@@ -315,31 +312,4 @@ begin -- wrapper
master_o.adr <= adr_out(29 downto 0) & "00";
dat_in <= master_i.dat;
gen_int_user_csr : if g_user_csr_ext = false generate
U_User_CSR : VME_User_CSR
generic map (
g_wb_data_width => g_wb_data_width
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
addr_i => user_csr_addr,
data_i => user_csr_data_out,
data_o => user_csr_data_in,
we_i => user_csr_we,
irq_vector_o => irq_vector,
irq_level_o => irq_level,
endian_o => endian,
time_i => x"0000000000",
bytes_i => x"0000"
);
end generate;
gen_ext_user_csr : if g_user_csr_ext = true generate
user_csr_data_in <= user_csr_data_i;
end generate;
user_csr_addr_o <= user_csr_addr;
user_csr_data_o <= user_csr_data_out;
user_csr_we_o <= user_csr_we;
end wrapper;
......@@ -78,55 +78,55 @@ package xvme64x_core_pkg is
------------------------------------------------------------------------------
component xvme64x_core
generic (
g_clock : integer;
g_wb_data_width : integer;
g_wb_addr_width : integer;
g_user_csr_ext : boolean;
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
g_program_id : std_logic_vector(7 downto 0);
g_ascii_ptr : std_logic_vector(23 downto 0);
g_beg_user_cr : std_logic_vector(23 downto 0);
g_end_user_cr : std_logic_vector(23 downto 0);
g_beg_cram : std_logic_vector(23 downto 0);
g_end_cram : std_logic_vector(23 downto 0);
g_beg_user_csr : std_logic_vector(23 downto 0);
g_end_user_csr : std_logic_vector(23 downto 0);
g_beg_sn : std_logic_vector(23 downto 0);
g_end_sn : std_logic_vector(23 downto 0);
g_f0_adem : std_logic_vector( 31 downto 0);
g_f0_amcap : std_logic_vector( 63 downto 0);
g_f0_xamcap : std_logic_vector(255 downto 0);
g_f0_dawpr : std_logic_vector( 7 downto 0);
g_f1_adem : std_logic_vector( 31 downto 0);
g_f1_amcap : std_logic_vector( 63 downto 0);
g_f1_xamcap : std_logic_vector(255 downto 0);
g_f1_dawpr : std_logic_vector( 7 downto 0);
g_f2_adem : std_logic_vector( 31 downto 0);
g_f2_amcap : std_logic_vector( 63 downto 0);
g_f2_xamcap : std_logic_vector(255 downto 0);
g_f2_dawpr : std_logic_vector( 7 downto 0);
g_f3_adem : std_logic_vector( 31 downto 0);
g_f3_amcap : std_logic_vector( 63 downto 0);
g_f3_xamcap : std_logic_vector(255 downto 0);
g_f3_dawpr : std_logic_vector( 7 downto 0);
g_f4_adem : std_logic_vector( 31 downto 0);
g_f4_amcap : std_logic_vector( 63 downto 0);
g_f4_xamcap : std_logic_vector(255 downto 0);
g_f4_dawpr : std_logic_vector( 7 downto 0);
g_f5_adem : std_logic_vector( 31 downto 0);
g_f5_amcap : std_logic_vector( 63 downto 0);
g_f5_xamcap : std_logic_vector(255 downto 0);
g_f5_dawpr : std_logic_vector( 7 downto 0);
g_f6_adem : std_logic_vector( 31 downto 0);
g_f6_amcap : std_logic_vector( 63 downto 0);
g_f6_xamcap : std_logic_vector(255 downto 0);
g_f6_dawpr : std_logic_vector( 7 downto 0);
g_f7_adem : std_logic_vector( 31 downto 0);
g_f7_amcap : std_logic_vector( 63 downto 0);
g_f7_xamcap : std_logic_vector(255 downto 0);
g_f7_dawpr : std_logic_vector( 7 downto 0)
g_clock_period : integer := c_clk_period;
g_wb_data_width : integer := c_wishbone_data_width;
g_wb_addr_width : integer := c_wishbone_address_width;
g_user_csr_ext : boolean := false;
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
g_board_id : std_logic_vector(31 downto 0) := c_svec_id;
g_revision_id : std_logic_vector(31 downto 0) := c_revision_id;
g_program_id : std_logic_vector(7 downto 0) := c_program_id;
g_ascii_ptr : std_logic_vector(23 downto 0) := x"000000";
g_beg_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_end_user_cr : std_logic_vector(23 downto 0) := x"000000";
g_beg_cram : std_logic_vector(23 downto 0) := x"001003";
g_end_cram : std_logic_vector(23 downto 0) := x"0013ff";
g_beg_user_csr : std_logic_vector(23 downto 0) := x"07ff33";
g_end_user_csr : std_logic_vector(23 downto 0) := x"07ff5f";
g_beg_sn : std_logic_vector(23 downto 0) := x"000000";
g_end_sn : std_logic_vector(23 downto 0) := x"000000";
g_f0_adem : std_logic_vector( 31 downto 0) := x"ff000000";
g_f0_amcap : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_f0_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f0_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f1_adem : std_logic_vector( 31 downto 0) := x"fff80000";
g_f1_amcap : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_f1_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f1_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f2_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f2_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f2_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f2_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f3_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f3_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f3_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f3_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f4_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f4_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f4_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f4_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f5_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f5_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f5_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f5_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f6_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f6_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f6_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f6_dawpr : std_logic_vector( 7 downto 0) := x"84";
g_f7_adem : std_logic_vector( 31 downto 0) := x"00000000";
g_f7_amcap : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_f7_xamcap : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_f7_dawpr : std_logic_vector( 7 downto 0) := x"84"
);
port (
clk_i : in std_logic;
......@@ -161,6 +161,9 @@ package xvme64x_core_pkg is
master_i : in t_wishbone_master_in;
irq_i : in std_logic;
irq_ack_o : out std_logic;
irq_level_i : in std_logic_vector( 7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector( 7 downto 0) := (others => '0');
endian_i : in std_logic_vector( 2 downto 0) := (others => '0');
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
......
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