vme_bus: add setup time.

e02c9e0f · Tristan Gingold · ef710744 · e02c9e0f
Commit e02c9e0f authored Jan 27, 2020 by Tristan Gingold
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Showing with 29 additions and 6 deletions

vme_bus.vhd hdl/rtl/vme_bus.vhd +29 -6

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--- a/hdl/rtl/vme_bus.vhd
+++ b/hdl/rtl/vme_bus.vhd
@@ -68,6 +68,15 @@ entity vme_bus is
    vme_iack_n_i    : in  std_logic;
    vme_iackout_n_o : out std_logic;

+    --  Setup and hold times for dtack (in number of cycles).
+    --  [3:0] is the hold time for 160MB/s
+    --  [7:4]        setup
+    --  [11:8]       hold          266MB/s
+    --  [15:12]      setup
+    --  [19:16]      hold          320MB/s
+    --  [23:20]      setup
+    data_timing     : in  std_logic_vector(23 downto 0) := x"11_22_22";
+
    -- WB signals
    wb_stb_o        : out std_logic;
    wb_ack_i        : in  std_logic;
@@ -222,9 +231,11 @@ architecture rtl of vme_bus is

  signal s_DS_latch_count           : unsigned (2 downto 0);

+  signal s_setup : unsigned(3 downto 0);
+
  -- WB FSM states
  type t_WBFSMstates is (
-	-- Wait until the Main FSM issues a WB cycle.
+	  -- Wait until the Main FSM issues a WB cycle.
    IDLE,

    -- Wait for WB reply
@@ -452,9 +463,14 @@ begin
              vme_odff_addr_dir  <= '1';
              vme_odff_data_dir  <= '1';

-              vme_dtack_async_ctrl <= '1';
+              if s_setup = 0 then
+                -- Do not assert dtack before setup cycles.
+                vme_dtack_async_ctrl <= '1';
+              else
+                s_setup <= s_setup - 1;
+              end if;

-              vme_odff_addr <= data_reg(63 downto 33);
+              vme_odff_addr    <= data_reg(63 downto 33);
              vme_odff_lword_n <= data_reg(32);
              vme_odff_data    <= data_reg(31 downto 0);
            end if;
@@ -479,7 +495,7 @@ begin
                vme_odff_addr_dir  <= '1';
                vme_odff_data_dir  <= '1';

-                if s_wb_done = '1' then
+                if s_wb_done = '1' and s_setup = 0 then
                  --  Prefetch.
                  s_wb_start <= '1';

@@ -501,6 +517,8 @@ begin
            end if;

          when LATCH_DS =>
+            -- At least one DS line is asserted.  Wait a little bit to check
+            -- if both are asserted or not.
            -- This state is necessary indeed the VME master can assert the
            -- DS lines not at the same time.
            vme_odff_dtack_oe <= '1';
@@ -528,7 +546,8 @@ begin
                s_mainFSMstate <= DTACK_LOW;

                if vme_idff_write_n = '1' then
-                  --  Can fetch the first data.
+                  --  Can fetch the first data. Cannot be done before
+                  --  because we need to know that this is a read access.
                  s_wb_start <= '1';
                end if;
              else
@@ -575,6 +594,7 @@ begin
            if s_conf_sel = '1' or s_wb_done = '1' or s_irq_sel = '1' then
              vme_odff_data_dir   <= vme_idff_write_n;

+              --  Put data (only enabled on read.)
              if g_VME32 then
                --  only for MBLT
                vme_odff_addr <= data_reg(63 downto 33);
@@ -638,11 +658,14 @@ begin
                vme_odff_addr_dir <= '0';
              else
                --  Any block transfer.
-                if g_VME32 and s_transferType = MBLT and s_MBLT_Data = '0' then
+                if g_VME32 and s_transferType = MBLT then
                  -- MBLT: end of address phase.
                  s_MBLT_Data <= '1';
                end if;

+                --  Load the setup counter.
+                s_setup <= unsigned (data_timing(7 downto 4));
+
                --  Keep same direction for data and address.
                s_mainFSMstate <= WAIT_FOR_DS;
              end if;