Commit e91bc332 authored by Tristan Gingold's avatar Tristan Gingold

vme64x: simplify again (remove swapper)

parent 7a9ed7cf
......@@ -110,15 +110,9 @@ architecture Behavioral of VME_Wb_master is
signal s_cyc : std_logic;
signal s_AckWithError : std_logic;
signal s_wbData_i : std_logic_vector(63 downto 0);
signal s_select : std_logic_vector(8 downto 0);
signal s_DATi_sample : std_logic_vector(g_WB_DATA_WIDTH-1 downto 0);
signal s_memAckWB_d1 : std_logic;
begin
s_select <= cardSel_i & sel_i;
s_wbData_i <= std_logic_vector(resize(unsigned(s_DATi_sample),s_wbData_i'length));
-- stb handler
process (clk_i)
begin
......@@ -148,7 +142,7 @@ begin
begin
if rising_edge(clk_i) then
RW_o <= RW_i;
s_AckWithError <=(memReq_i and cardSel_i and BERRcondition_i);
s_AckWithError <= (memReq_i and cardSel_i and BERRcondition_i);
end if;
end process;
......@@ -187,38 +181,38 @@ begin
end if;
end process;
process (s_select, s_wbData_i)
process (sel_i, s_wbData_i)
begin
case s_select is
when "100000010" =>
case sel_i is
when "00000010" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(15 downto 0)) srl 8, locDataOut_o'length));
when "100000100" =>
when "00000100" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(23 downto 0)) srl 16, locDataOut_o'length));
when "100001000" =>
when "00001000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(31 downto 0)) srl 24, locDataOut_o'length));
when "100010000" =>
when "00010000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(39 downto 0)) srl 32, locDataOut_o'length));
when "100100000" =>
when "00100000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(47 downto 0)) srl 40, locDataOut_o'length));
when "101000000" =>
when "01000000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(55 downto 0)) srl 48, locDataOut_o'length));
when "110000000" =>
when "10000000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(63 downto 0)) srl 56, locDataOut_o'length));
when "100001100" =>
when "00001100" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(31 downto 0)) srl 16, locDataOut_o'length));
when "100110000" =>
when "00110000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(47 downto 0)) srl 32, locDataOut_o'length));
when "111000000" =>
when "11000000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(63 downto 0)) srl 48, locDataOut_o'length));
when "100000001" =>
when "00000001" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(7 downto 0)), locDataOut_o'length));
when "100000011" =>
when "00000011" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(15 downto 0)), locDataOut_o'length));
when "100001111" =>
when "00001111" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(31 downto 0)), locDataOut_o'length));
when "111110000" =>
when "11110000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(63 downto 0)) srl 32, locDataOut_o'length));
when "111111111" =>
when "11111111" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(63 downto 0)), locDataOut_o'length));
when others =>
locDataOut_o <= (others => '0');
......@@ -236,90 +230,20 @@ begin
end if;
end process;
process (sel_i)
begin
if sel_i = "10000000" or sel_i = "01000000" or sel_i = "00100000" or
sel_i = "00010000" or sel_i = "11000000" or sel_i = "00110000" or
sel_i = "11110000"
then
s_shift_dx <= '1';
else
s_shift_dx <= '0';
end if;
end process;
process (clk_i)
begin
if rising_edge(clk_i) then
case sel_i is
when "10000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24, g_WB_DATA_WIDTH));
when "01000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00100000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8, g_WB_DATA_WIDTH));
when "00010000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "00001000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24, g_WB_DATA_WIDTH));
when "00000100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00000010" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8, g_WB_DATA_WIDTH));
when "00000001" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "11000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "00001100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16, g_WB_DATA_WIDTH));
when "00000011" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "11110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "00001111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when "11111111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i), g_WB_DATA_WIDTH));
when others => null;
end case;
if s_shift_dx = '1' then
WbSel_o <= sel_i(7 downto 4);
else
WBdata_o <= locDataInSwap_i(31 downto 0);
WbSel_o <= sel_i(3 downto 0);
end if;
end if;
end process;
process (s_select, s_wbData_i)
begin
case s_select is
when "100000010" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(15 downto 0)) srl 8, locDataOut_o'length));
when "100000100" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(23 downto 0)) srl 16, locDataOut_o'length));
when "100001000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(31 downto 0)) srl 24, locDataOut_o'length));
when "100010000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(7 downto 0)), locDataOut_o'length));
when "100100000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(15 downto 0)) srl 8, locDataOut_o'length));
when "101000000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(23 downto 0)) srl 16, locDataOut_o'length));
when "110000000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(31 downto 0)) srl 24, locDataOut_o'length));
when "100001100" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(31 downto 0)) srl 16, locDataOut_o'length));
when "100110000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(15 downto 0)), locDataOut_o'length));
when "111000000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(31 downto 0)) srl 16, locDataOut_o'length));
when "100000001" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(7 downto 0)), locDataOut_o'length));
when "100000011" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(15 downto 0)), locDataOut_o'length));
when "100001111" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(31 downto 0)), locDataOut_o'length));
when "111110000" =>
locDataOut_o <= std_logic_vector(resize(unsigned(s_wbData_i(31 downto 0)), locDataOut_o'length));
when others =>
locDataOut_o <= (others => '0');
end case;
end process;
locDataOut_o <= s_wbData_i;
end generate gen32;
err_o <= err_i;
rty_o <= rty_i;
memAckWb_o <= memAckWB_i or s_AckWithError or rty_i;
-- This process registers the WB data input; this is a warranty that this
-- data will be stable during all the time the VME_bus component needs to
-- transfers its to the VME bus.
......@@ -327,9 +251,12 @@ begin
begin
if rising_edge(clk_i) then
if memAckWB_i = '1' then
s_DATi_sample <= wbData_i;
s_wbData_i <= (others => '0');
s_wbData_i(wbData_i'range) <= wbData_i;
end if;
s_memAckWb_d1 <= memAckWB_i or s_AckWithError or rty_i;
end if;
end process;
memAckWb_o <= s_memAckWB_d1;
end Behavioral;
This diff is collapsed.
......@@ -64,42 +64,34 @@ entity xvme64x_core is
g_F0_ADEM : std_logic_vector( 31 downto 0) := x"ff000000";
g_F0_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_F0_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F0_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F1_ADEM : std_logic_vector( 31 downto 0) := x"fff80000";
g_F1_AMCAP : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_F1_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F1_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F2_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F2_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F2_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F2_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F3_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F3_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F3_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F3_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F4_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F4_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F4_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F4_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F5_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F5_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F5_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F5_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F6_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F6_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F6_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F6_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F7_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F7_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F7_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F7_DAWPR : std_logic_vector( 7 downto 0) := x"84"
);
port (
......@@ -150,25 +142,7 @@ entity xvme64x_core is
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f0_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0')
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0')
);
end xvme64x_core;
......@@ -201,35 +175,27 @@ begin -- wrapper
g_END_SN => g_END_SN,
g_F0_ADEM => g_F0_ADEM,
g_F0_AMCAP => g_F0_AMCAP,
g_F0_XAMCAP => g_F0_XAMCAP,
g_F0_DAWPR => g_F0_DAWPR,
g_F1_ADEM => g_F1_ADEM,
g_F1_AMCAP => g_F1_AMCAP,
g_F1_XAMCAP => g_F1_XAMCAP,
g_F1_DAWPR => g_F1_DAWPR,
g_F2_ADEM => g_F2_ADEM,
g_F2_AMCAP => g_F2_AMCAP,
g_F2_XAMCAP => g_F2_XAMCAP,
g_F2_DAWPR => g_F2_DAWPR,
g_F3_ADEM => g_F3_ADEM,
g_F3_AMCAP => g_F3_AMCAP,
g_F3_XAMCAP => g_F3_XAMCAP,
g_F3_DAWPR => g_F3_DAWPR,
g_F4_ADEM => g_F4_ADEM,
g_F4_AMCAP => g_F4_AMCAP,
g_F4_XAMCAP => g_F4_XAMCAP,
g_F4_DAWPR => g_F4_DAWPR,
g_F5_ADEM => g_F5_ADEM,
g_F5_AMCAP => g_F5_AMCAP,
g_F5_XAMCAP => g_F5_XAMCAP,
g_F5_DAWPR => g_F5_DAWPR,
g_F6_ADEM => g_F6_ADEM,
g_F6_AMCAP => g_F6_AMCAP,
g_F6_XAMCAP => g_F6_XAMCAP,
g_F6_DAWPR => g_F6_DAWPR,
g_F7_ADEM => g_F7_ADEM,
g_F7_AMCAP => g_F7_AMCAP,
g_F7_XAMCAP => g_F7_XAMCAP,
g_F7_DAWPR => g_F7_DAWPR
)
port map (
......@@ -288,25 +254,7 @@ begin -- wrapper
irq_i => irq_i,
irq_ack_o => irq_ack_o,
irq_vector_i => irq_vector_i,
irq_level_i => irq_level_i,
f0_faf_ader_i => f0_faf_ader_i,
f1_faf_ader_i => f1_faf_ader_i,
f2_faf_ader_i => f2_faf_ader_i,
f3_faf_ader_i => f3_faf_ader_i,
f4_faf_ader_i => f4_faf_ader_i,
f5_faf_ader_i => f5_faf_ader_i,
f6_faf_ader_i => f6_faf_ader_i,
f7_faf_ader_i => f7_faf_ader_i,
f0_dfs_adem_i => f0_dfs_adem_i,
f1_dfs_adem_i => f1_dfs_adem_i,
f2_dfs_adem_i => f2_dfs_adem_i,
f3_dfs_adem_i => f3_dfs_adem_i,
f4_dfs_adem_i => f4_dfs_adem_i,
f5_dfs_adem_i => f5_dfs_adem_i,
f6_dfs_adem_i => f6_dfs_adem_i,
f7_dfs_adem_i => f7_dfs_adem_i
irq_level_i => irq_level_i
);
master_o.dat <= dat_out(31 downto 0);
......
entity top_tb is
generic (scenario : natural range 0 to 3 := 3);
generic (scenario : natural range 0 to 3 := 1);
end;
library ieee;
......@@ -948,6 +948,8 @@ begin
case scenario is
when 0 =>
-- Disp CR/CSR
-- Read CSR
read8_conf (x"7_FFFF", d8);
assert d8 = slave_ga & "000"
......@@ -962,6 +964,8 @@ begin
Dump_CR;
when 1 =>
-- WB data access
-- Check ADER is 0
read8_conf (x"7_ff63", d8);
assert d8 = x"00" report "bad initial ADER0 value" severity error;
......@@ -997,6 +1001,7 @@ begin
read32 (x"56_00_00_14", c_AM_A32, d32);
assert d32 = x"0000_0500" report "bad read at 014" severity error;
-- WB write
write8 (x"56_00_00_14", c_AM_A32, x"1f");
read32 (x"56_00_00_14", c_AM_A32, d32);
assert d32 = x"1f00_0500" report "bad read at 014 (2)" severity error;
......
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