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VME64x core
Commit fa34d06e authored by Tristan Gingold's avatar Tristan Gingold
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Add g_WB_GRANULARITY and removed default value of g_CLOCK_PERIOD.

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doc/vme64x_core-ug.txt
View file @ fa34d06e
VME64x to WB core User Guide
============================
:Author: Tristan Gingold
:Date: 2017-12-12
:Date: 2017-12-14
:Revision: 2.0
Introduction
......@@ -240,13 +240,11 @@ must be set by the user and is used for synchronization of the VME DS
signal.
Generic `g_DECODE_AM` enables/disables the AM field of ADER when
decoding
address. When it is set to false, behavior of this core is consistent
with its previous versions. In particlular, when false, the AM field
of ADER is not used when decoding address, so the core will recognize
any access allowed by the corresponding AMCAP. New designs should set
this
generic to true.
decoding address. When it is set to false, behavior of this core is
consistent with its previous versions. In particlular, when false, the
AM field of ADER is not used when decoding address, so the core will
recognize any access allowed by the corresponding AMCAP. New designs
should set this generic to true.
Generic `g_USER_CSR_EXT` enables/disables user-defined CSR. The
interface with the user CSR is a very simple synchronous SRAM (signals
......@@ -256,10 +254,17 @@ input port `irq_level_i` and `irq_vector_i` are used by the interrupt
controller to define the irq level and vector (otherwise they are read
from the default user CSR registers).
Generic `g_WB_GRANULARITY` specifies the address granularity of the
wishbone bus. The value is one of:
* `WORD`: addresses represent words, so VME address 4, 5, 6 and 7 are
translated to WB address 1.
* `BYTE`: addresses represents bytes, so VME addresses 4, 5, 6 and 7 are
translated to WB address 4. The two LSB of WB address are always 0.
The other generics define values in the CSR. The package `vme64x_pkg`
defines default constants for these values, see the VME64x specification
for
details about these values:
defines default constants for these values, see the VME64x
specification for details about these values:
* `g_MANUFACTURER_ID` provides the manufacturer ID,
* `g_BOARD_ID` provides the board ID,
......
hdl/rtl/vme64x_core.vhd
View file @ fa34d06e
......@@ -11,9 +11,10 @@ use work.vme64x_pkg.all;
entity vme64x_core is
generic (
g_clock_period : integer;
g_clock_period : natural;
g_decode_am : boolean;
g_user_csr_ext : boolean;
g_wb_granularity : t_wishbone_address_granularity;
g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0);
......@@ -110,6 +111,7 @@ begin
g_clock_period => g_clock_period,
g_decode_am => g_decode_am,
g_user_csr_ext => g_user_csr_ext,
g_wb_granularity => g_wb_granularity,
g_manufacturer_id => g_manufacturer_id,
g_board_id => g_board_id,
g_revision_id => g_revision_id,
......
hdl/rtl/vme64x_pkg.vhd
View file @ fa34d06e
......@@ -182,9 +182,10 @@ package vme64x_pkg is
-- Refer to the entity declaration (xvme64x_core.vhd) for comments.
component xvme64x_core
generic (
g_CLOCK_PERIOD : integer := -1;
g_CLOCK_PERIOD : natural;
g_DECODE_AM : boolean := true;
g_USER_CSR_EXT : boolean := false;
g_WB_GRANULARITY : t_wishbone_address_granularity;
g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
g_BOARD_ID : std_logic_vector(31 downto 0);
......
hdl/rtl/vme_bus.vhd
View file @ fa34d06e
......@@ -29,10 +29,12 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pkg.all;
use work.wishbone_pkg.all;
entity vme_bus is
generic (
g_CLOCK_PERIOD : integer
g_CLOCK_PERIOD : integer;
g_WB_GRANULARITY : t_wishbone_address_granularity
);
port (
clk_i : in std_logic;
......@@ -711,7 +713,9 @@ begin
VME_RETRY_OE_o <= '0';
-- WB Master
wb_adr_o <= "00" & s_vme_addr_reg(31 downto 2);
with g_WB_GRANULARITY select
wb_adr_o <= "00" & s_vme_addr_reg(31 downto 2) when WORD,
s_vme_addr_reg(31 downto 2) & "00" when BYTE;
wb_we_o <= not s_WRITElatched_n;
wb_dat_o <= s_locDataIn(31 downto 0);
......
hdl/rtl/xvme64x_core.vhd
View file @ fa34d06e
......@@ -11,27 +11,6 @@
-- This core implements an interface to transfer data between the VMEbus and
-- the WBbus. This core is a Slave in the VME side and Master in the WB side.
--
-- The main blocks:
--
-- _______________________vme64x_core_______________________
-- | ________________ ________ ___________________ |
-- |___ | | | | | | |
-- | | | VME Bus | | Funct | | | |
-- | | | | | Match | | VME to WB FIFO | |
-- | S | | | | | | | (not implemented) | |
-- V | A | | VME | WB | |________| | | | W
-- M | M | | slave | master | ________ | | | B
-- E | P | | | | | | | | |
-- | L | | | | | CR/CSR | | | | B
-- B | I | | | | | Space | |___________________| | U
-- U | N | | | |________| ___________________ | S
-- S | G | | | ________ | | |
-- | | | | | | | IRQ Controller | |
-- |___| | | | User | | | |
-- | | | | CSR | | | |
-- | |________________| |________| |___________________| |
-- |_________________________________________________________|
--
-- All the output signals on the WB bus are registered.
-- The Input signals from the WB bus aren't registered indeed the WB is a
-- synchronous protocol and some registers in the WB side will introduce a
......@@ -61,9 +40,8 @@ use work.vme64x_pkg.all;
entity xvme64x_core is
generic (
-- Clock period (ns). Used for DS synchronization. The default value
-- will genrate an assertion failure.
g_CLOCK_PERIOD : integer := -1;
-- Clock period (ns). Used for DS synchronization. A value is required.
g_CLOCK_PERIOD : natural;
-- Consider AM field of ADER to decode addresses. This is what the VME64x
-- standard says. However, for compatibility with previous implementations
......@@ -74,6 +52,13 @@ entity xvme64x_core is
-- Use external user CSR
g_USER_CSR_EXT : boolean := false;
-- Address granularity on the WB bus. Value can be:
-- WORD: VME address bits 31:2 are translated to WB address bits 29:0,
-- the WB data represents bytes for VME address bits 1:0.
-- BYTE: VME address bits 31:2 are translated to WB address bits 31:2,
-- WB address bits 1:0 are always 0.
g_WB_GRANULARITY : t_wishbone_address_granularity;
-- Manufacturer ID: IEEE OUID
-- e.g. CERN is 0x080030
g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
......@@ -289,8 +274,8 @@ begin
------------------------------------------------------------------------------
inst_vme_bus : entity work.vme_bus
generic map (
g_CLOCK_PERIOD => g_CLOCK_PERIOD
)
g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_WB_GRANULARITY => g_WB_GRANULARITY)
port map (
clk_i => clk_i,
rst_n_i => s_reset_n,
......@@ -350,8 +335,7 @@ begin
INT_Level_i => s_irq_level,
INT_Vector_i => s_irq_vector,
irq_pending_i => s_irq_pending,
irq_ack_o => s_irq_ack
);
irq_ack_o => s_irq_ack);
s_reset_n <= rst_n_i and s_VME_RST_n;
rst_n_o <= s_reset_n and (not s_module_reset);
......
hdl/testbench/simple_tb/top_tb.vhd
View file @ fa34d06e
......@@ -37,9 +37,11 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use work.vme64x_pkg.all;
use std.textio.all;
use work.vme64x_pkg.all;
use work.wishbone_pkg.all;
architecture behaviour of top_tb is
subtype cfg_addr_t is std_logic_vector (19 downto 0);
subtype byte_t is std_logic_vector (7 downto 0);
......@@ -263,6 +265,7 @@ begin
vme64xcore: entity work.vme64x_core
generic map (g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_DECODE_AM => (g_SCENARIO /= 9),
g_WB_GRANULARITY => WORD,
g_USER_CSR_EXT => false,
g_MANUFACTURER_ID => c_CERN_ID,
......
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