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VME64x core
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VME64x core
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fd6dce67
Commit
fd6dce67
authored
Aug 17, 2018
by
Tristan Gingold
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vme_bus: wait for ack = 0 between MBLT WB xfer.
parent
c50928bb
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vme_bus.vhd
hdl/rtl/vme_bus.vhd
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hdl/rtl/vme_bus.vhd
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fd6dce67
...
...
@@ -584,9 +584,16 @@ begin
end
if
;
when
MEMORY_PAUSE
=>
-- Do not wait until ACK is 0, as ACK can be always 1.
wb_stb_o
<=
'1'
;
s_mainFSMstate
<=
MEMORY_REQ
;
-- Wait until ACK is 0. Strictly speaking, this is not needed
-- according to WB specs.
wb_stb_o
<=
'0'
;
if
wb_ack_i
=
'0'
then
wb_stb_o
<=
'1'
;
s_mainFSMstate
<=
MEMORY_REQ
;
else
s_mainFSMstate
<=
MEMORY_PAUSE
;
end
if
;
when
DATA_TO_BUS
=>
VME_DTACK_OE_o
<=
'1'
;
...
...
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