VME64x core:3125363dd29db8f9b65cc28e3594ea485e04088b commitshttps://ohwr.org/project/vme64x-core/commits/3125363dd29db8f9b65cc28e3594ea485e04088b2017-11-27T08:09:45Zhttps://ohwr.org/project/vme64x-core/commit/3125363dd29db8f9b65cc28e3594ea485e04088bvme_bus: address reset renaming.2017-11-27T08:09:45ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/9174e0e748aee7ba20589f6f8f66131ecde06462Address issues in vme64x_pkg.2017-11-27T08:01:12ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/593dbebd0029c40ab5c1a288f40d9362271b1c7dvme_irq_controller: rename reset_n_i to rst_n_i2017-11-27T07:50:54ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/0343da4d82f69e4fa8764209fe29f4c099807dc9Update review status.2017-11-27T07:48:50ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/fa8b16ac4f06f4325ec6cb213be88aa8a68fc66aUpdate review.2017-11-27T07:41:05ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/5f73a25cb21edb0a4a7e62ced38f172f8e4e2e73Get rid of vme_sysfail (unused).2017-11-27T07:39:44ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/df1f3a4ef1cffa7bfa53d7ce51fd4d4d3ffa7553Handle all A24 and A32 requests by default.2017-11-27T07:36:08ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/d1f969c884960b12972c10bd4efeb4fcd16b9e23xvme64x_core is now the top-level entity, vme64x_core is a wrapper.2017-11-24T13:30:29ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/22994dc67e2c3f966d81bff8a03f1aab3e82272aRework top-level generics.2017-11-24T10:56:27ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/ebbf128722203f00a383493707ca8d92cc8b7251Merge xvme64x_core_pkg into vme64x_pkg.2017-11-24T10:50:38ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/b67a89296611fd7a73edba509f3d7e3c299fe7bfUpdate review status.2017-11-14T09:36:57ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/20f51d45431051dfadaee6d3024f92680144e263Rename units (to follow file names).2017-11-14T09:33:24ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/af1eb06a73e389d3c94d9ff04c5035af01f47da5Rename file names (to lower case).2017-11-14T09:19:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/0508124026d14a3a3b9fbb50bb26fa068e17b8afAdd README, adjust Manifest.py2017-11-14T09:08:56ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/dc69f9301e71563ea61dd9438389a43f8c21b609[submodules] added general-cores as submodules2017-11-14T08:56:30ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/3d3ea084058e1479f5da5a7c7e906f1ba6cd43a2Remove .gitmodules before cherry-pick.2017-11-14T08:56:15ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/5be6b4bef82d31ace9112aa5863ab7a109765eaeRestore vme64x_bfm.2017-11-14T08:50:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/78a25d2cfb076f5228094a71256d4ea4d288449eRename sim to testbench2017-11-14T08:47:43ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/5cf647bf680df44a239d088cd926542f1c6308e7Remove general-cores.2017-11-14T08:46:47ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/131c5766445760f083992e3a829984bdda5a46e0Update review document after 2017-11-13 review.2017-11-14T08:41:56ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/34239178af11cd512668e457c3eeed5a443c180e[sim] added run.do script to run scenario 1.2017-11-13T13:01:59ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/3ebc1916c69040a1d8bfb618ba60af93dbedd2e7[sim] added wave.do2017-11-13T13:01:42ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/9076173e6fce0827b750be2dbf6107af33351880[desc] small corrections to the description in the VME64xCore_Top.vhd fiel2017-11-13T12:59:19ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/159267795c9d2ee0979fce62e7e0a0698cdfe6ca[desc] small corrections to VME_IRQ_Controller.vhd file2017-11-13T12:59:13ZMaciej Lipinskimaciej.lipinski@cern.chhttps://ohwr.org/project/vme64x-core/commit/f9505f1530d0ccb59aec292e4fde27272d3eee10Greg review update.2017-11-13T12:52:23ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/250f7da5f73aad9e6cefbb0eaff7ad02b8d32643Remove unused vme64x_bfm.2017-11-13T08:57:49ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/7362766427f308585f29d8819c45cc919c363386Add reviews.2017-11-13T08:55:07ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/557e12cf65484a027344339dbd09e543463d1b4dRemove oudated file.2017-11-13T08:52:40ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/829ccb6f572aa052680b362606277c19d26966a1Rename doc directory.2017-11-13T08:50:57ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/a1bea3a811b2825b8531f269fd479f334693f226use local constants for wishbone address and data width generics of xvme64x_c...2017-11-13T08:47:05ZDimitris LampridisDimitris.Lampridis@cern.chuse local constants for wishbone address and data width generics of xvme64x_core (same as VME64xCore_Top)
https://ohwr.org/project/vme64x-core/commit/e109be6f764a4c5d48d2a72cf1599ae7db83a5ebsim: improve SNR of terminal output2017-11-13T08:47:05ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/3bc0f999558db129b2405b8d4578b9184fed0903sim: no need to invoke modelsim gui at the end of make2017-11-13T08:47:04ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/756ef1a8cca463fda1485e6257c259870971a8acsim: drop "bash-ism" from run_all.sh2017-11-13T08:47:04ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/8593f0498c1788b2773f5eb093b97411925f4b86sim: add general-cores as submodule in order to pin it to specific commit2017-11-13T08:47:04ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/6afbfb63ed8cb5298d65e9e023bdd19dd9e152ebsim: ignore files auto-generated by Modelsim2017-11-13T08:47:03ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/c280586a79d3238e3aa0019506ee5a6af9327f06fix minor syntax error in specifications2017-11-06T10:11:34ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/18674fd36ead6b79ff9121fc1a8103c00fcc77f8Remove non-ASCII characters in order to make all sources plain 'ASCII test'2017-11-06T09:02:43ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/vme64x-core/commit/f9a19cab0e175eb7a8f3d286f2cff2c9b3a73b18Fix association order (and remove one extra useless generic).2017-10-25T12:14:46ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/f210991d50edd758e1bbf1754bb03484e7d81507Add script to run all the test cases.2017-10-25T12:14:11ZTristan Gingoldtristan.gingold@cern.chhttps://ohwr.org/project/vme64x-core/commit/7c71c06b59654e8267f4f12b8fa40726dff8ffc5Implement g_DECODE_AM (for backward compatibility).2017-10-24T09:58:50ZTristan Gingoldtristan.gingold@cern.ch