Programming languages used in this repository

  •   VHDL
    88.47 %
  •   SystemVerilog
    7.41 %
  •   Makefile
    2.06 %
  •   Stata
    0.73 %
  •   Python
    0.53 %
  •   Shell
    0.44 %
  •   Verilog
    0.36 %

Commit statistics for 3ed18b0674458b79d7660606a33afe2789204d39 Mar 31 - Nov 27

  • Total: 356 commits
  • Average per day: 0.1 commits
  • Authors: 16

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