Programming languages used in this repository

  •   VHDL
    85.65 %
  •   SystemVerilog
    9.6 %
  •   Makefile
    2.67 %
  •   Stata
    0.94 %
  •   Verilog
    0.47 %
  •   Python
    0.38 %
  •   Shell
    0.29 %

Commit statistics for 78cac8713658de449dcccbce5a5d35131461fc34 Mar 31 - Nov 29

  • Total: 400 commits
  • Average per day: 0.1 commits
  • Authors: 18

Commits per day of month

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