Programming languages used in this repository

  •   VHDL
    88.78 %
  •   SystemVerilog
    7.21 %
  •   Makefile
    2.0 %
  •   Stata
    0.71 %
  •   Python
    0.52 %
  •   Shell
    0.43 %
  •   Verilog
    0.35 %

Commit statistics for 7c71c06b59654e8267f4f12b8fa40726dff8ffc5 Mar 31 - Oct 24

  • Total: 315 commits
  • Average per day: 0.1 commits
  • Authors: 15

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