Programming languages used in this repository

  •   VHDL
    88.39 %
  •   SystemVerilog
    7.45 %
  •   Makefile
    2.07 %
  •   Stata
    0.73 %
  •   Python
    0.54 %
  •   Shell
    0.45 %
  •   Verilog
    0.37 %

Commit statistics for 8aaa3368d5de072be25d3e7b51fde0e393f82a16 Mar 31 - Nov 27

  • Total: 362 commits
  • Average per day: 0.1 commits
  • Authors: 16

Commits per day of month

Commits per weekday

Commits per day hour (UTC)