Programming languages used in this repository

  •   VHDL
    85.65 %
  •   SystemVerilog
    9.6 %
  •   Makefile
    2.67 %
  •   Stata
    0.94 %
  •   Verilog
    0.47 %
  •   Python
    0.38 %
  •   Shell
    0.29 %

Commit statistics for a2ee4ac44503153b30767970d1ee64cc640880b4 Mar 31 - Oct 25

  • Total: 394 commits
  • Average per day: 0.1 commits
  • Authors: 17

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