Programming languages used in this repository

  •   VHDL
    88.78 %
  •   SystemVerilog
    7.21 %
  •   Makefile
    2.0 %
  •   Stata
    0.71 %
  •   Python
    0.52 %
  •   Shell
    0.43 %
  •   Verilog
    0.35 %

Commit statistics for a8ed013550646a9d44e876a0af8a9c6ec0109df1 Mar 31 - Dec 13

  • Total: 378 commits
  • Average per day: 0.1 commits
  • Authors: 16

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