Programming languages used in this repository

  •   VHDL
    88.78 %
  •   SystemVerilog
    7.21 %
  •   Makefile
    2.0 %
  •   Stata
    0.71 %
  •   Python
    0.52 %
  •   Shell
    0.43 %
  •   Verilog
    0.35 %

Commit statistics for b98546cabf08e0b151f9e6fa10c8e78f905f47f4 Mar 31 - Nov 30

  • Total: 365 commits
  • Average per day: 0.1 commits
  • Authors: 16

Commits per day of month

Commits per weekday

Commits per day hour (UTC)