Programming languages used in this repository

  •   VHDL
    85.65 %
  •   SystemVerilog
    9.6 %
  •   Makefile
    2.67 %
  •   Stata
    0.94 %
  •   Verilog
    0.47 %
  •   Python
    0.38 %
  •   Shell
    0.29 %

Commit statistics for fa34d06e35ca0bfad8eac24aa51713e81639da64 Mar 31 - Dec 14

  • Total: 380 commits
  • Average per day: 0.1 commits
  • Authors: 16

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