Programming languages used in this repository

  •   VHDL
    87.14 %
  •   SystemVerilog
    8.24 %
  •   Makefile
    2.29 %
  •   Stata
    0.81 %
  •   Python
    0.64 %
  •   Shell
    0.48 %
  •   Verilog
    0.41 %

Commit statistics for master Mar 31 - Nov 14

  • Total: 410 commits
  • Average per day: 0.1 commits
  • Authors: 18

Commits per day of month

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