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Remove the glitch observed on dtack in MBLT mode (seen on Dab64x at 40MHz with MEN-A20).

Mathieu Saccani requested to merge msaccani/vme64x-core-msaccani:patch-2 into master

A glitch is observed in simulation on dtack during MBLT read transfers, after the address acknowledgment and before the first data reply. The VME master then takes the glitch as the first data. Observed on target on a Dab64x board (Stratix at 40MHz) with a MEN-A20. Observed in simulation with VFC-HD (ArriaV at 125MHz) but filtered somehow on target (with MEN-A25).

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