During October to December 2017, the core (version 2) was tested on a SVEC card with the MEN A20 and MEN A25 masters.
This very core is used in the accelerators of CERN, is used in various configurations and is proven to be stable in many complex environments.
Q: How to port a design from v1.0 to v2.0?
The official top level entity for the vme64x core is xvme64x_core,
which has the vme, wb and configuration grouped in
The VME signals berr_n and irq_n are now active when set to '0' (like
on a VME bus), while in version 1.0 they followed the polarity of the
The generic g_WB_GRANULARITY was added in v2.0. For compatibility, it
should be set to BYTE if the vme64x_core is instantiated and to WORD if
the xvme64x_core is instantiated.
For software compatibility, AM matching should be disabled by setting
generic g_DECODE_AM to false.
Q: In which FPGA is it possible to fit the vme64x core?
On the SVEC card (Spartan 6), the core needs less than 750 registers.
We are testing the core in the following FPGA:
You can also fit the vme64x core in a smaller FPGA like the Spartan 6
XC6SLX9, package: FTG 256.
It depends on your WB application.
Q: What are the VME address modifiers supported by the core?
A24: AM 0x38 to 0x3f
A32: AM 0x08 to 0x0f
Q: I use the SVEC. How can I change the base address by writing appropriate values in some registers (ADER, ADEM, and possibly others)?
Write the ADER registers with the address base and the AM.
In addition, the code of svec_setup_csr() in the svec device
driver can also be
very helpful in understanding how you can do the configuration by
writing to the Address Relocation Registers.