Commit 1879f91d authored by Maciej Lipinski's avatar Maciej Lipinski

squeezed the article and updated figures

parent 64cf009a
......@@ -5,14 +5,9 @@
\usepackage{color, colortbl}
\usepackage{color,array}
\usepackage{hhline}
\graphicspath{ {../../figures/} }
\addtolength{\itemsep}{-0.05in}
\addtolength{\textfloatsep}{-0.05in}
\addtolength{\partopsep}{-0.02in}
\begin{document}
\title{White Rabbit clock characteristics }
\author{
......@@ -27,7 +22,11 @@
\IEEEauthorblockN{Paolo Ferrari}
\IEEEauthorblockN{Stefano Rinaldi}
\IEEEauthorblockA{University of Brescia, Italy}
\vspace{-4cm}}
}
\begin{document}
\maketitle
......@@ -123,18 +122,18 @@ GM, without intervention of the PTP protocol. The PTP
measurement of link-delay and offset from the master is used only to adjust the value of the
\textit{time counter} and the phase of the \textit{local PTP clock} of the WR node B.
The process of synchronizing a WR node B to a WR node A with is summarized as follows:
\begin{enumerate}
\item the \textit{local PTP clock} of the node B is syntonized to its \textit{L1 rx clock signal},
\item the link-delay and the offset from the master between A and B are measured,
\item the value of the \textit{time counter} of node B is corrected,
\item the offset from the master between A and B that is below the \textit{time counter}
resolution is corrected by phase-shifting the the \textit{local PTP clock} of the
node B,
\item the phase-alignment between the \textit{local PTP clocks} of the two nodes is
maintained by adjusting the phase of the \textit{clock PTP clock} at the node B
using PTP measurements.%, so-called \textit{phase tracking}.
\end{enumerate}
% The process of synchronizing a WR node B to a WR node A with is summarized as follows:
% \begin{enumerate}
% \item the \textit{local PTP clock} of the node B is syntonized to its \textit{L1 rx clock signal},
% \item the link-delay and the offset from the master between A and B are measured,
% \item the value of the \textit{time counter} of node B is corrected,
% \item the offset from the master between A and B that is below the \textit{time counter}
% resolution is corrected by phase-shifting the the \textit{local PTP clock} of the
% node B,
% \item the phase-alignment between the \textit{local PTP clocks} of the two nodes is
% maintained by adjusting the phase of the \textit{clock PTP clock} at the node B
% using PTP measurements.%, so-called \textit{phase tracking}.
% \end{enumerate}
The synchronisation in WR is maintained by adjusting the phase (phase-steering)
rather than manipulating the \textit{time counter} value. The WR PLL not only syntonizes the \textit{local PTP clock} to the recovered
\textit{L1 rx clock signal} but also maintains desired phase offset between these two
......@@ -302,12 +301,13 @@ and jitter tolerance. Fig.~\ref{fig:wanderTransfer1} shows that the transfer fun
WR switch has bandwidth of 35Hz and a phase gain of 3.3dB at 16Hz while the ITU-T G.8262
requires gain smaller than 0.2dB and bandwidth 1-10Hz for EEC-Option~1, 0.1Hz
for EEC-Option~2.
\vspace{-0.2cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{measurements/WRclockChar/WanderGen1.jpg}
\caption{Wander generation of the WR switch.}
\label{fig:WanderGen1}
\end{figure}
\end{figure}\vspace{-0.5cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.3\textwidth]{measurements/WRclockChar/wanderTransfer1.jpg}
......@@ -326,12 +326,12 @@ The section that follows characterizes L1 syntonisation using phase noise analy
The phase noise of frequency transfer through WR network is measured to evaluate the
current performance and identify potential improvements. The measurement is done
at each state of a linear daisy chain of 3 WR switches in a setup depicted in Fig.~\ref{fig:phaseNoise-setup}.
\begin{figure}[!ht]
\begin{figure}[!ht]\vspace{-0.5cm}
\centering
\includegraphics[width=0.28\textwidth]{measurements/WRclockChar/phaseNoise-setup.jpg}
\caption{Phase noise measurement.}
\label{fig:phaseNoise-setup}
\end{figure}\vspace{-0.2cm}
\end{figure}\vspace{-0.3cm}
The measurement setup includes CS4000 Cesium Frequency Standard (Cs),
Symmetricom 3120A High-Performance Phase Noise Test Probe, and 3 WR switches.
......@@ -342,15 +342,16 @@ the WR switches. This output provides 10MHz clock signal derived from the 62.5MH
This setup is used to measure phase noise of the of \textit{local PTP clock signal}
at the GM WR switch (GM), the WR switch 1 (SW1) and the WR switch 2 (SW2).
Fig.~\ref{fig:noiseTransfer} depicts results of these three measurements and indicates the
estimated phase noise floor. The noise floor is the combined noise estimated by 3120A and the
probe noise.
Fig.~\ref{fig:noiseTransfer} depicts results of these three measurements.
% and indicates the
% estimated phase noise floor. The noise floor is the combined noise estimated by 3120A and the
% probe noise.
\begin{figure}[!ht]
\centering
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/noiseTransfer.jpg}
\caption{Phase noise.}
\label{fig:noiseTransfer}
\end{figure}%\vspace{-0.5cm}
\end{figure}\vspace{-0.3cm}
The effect of gain peaking is clearly visible in the graph. The increase of
phase noise in the 1Hz-10Hz region suggests possible phase noise leaking from the voltage
controlled oscillator (VM53S3). Table~\ref{tab:phaseNoise}
......@@ -358,6 +359,13 @@ provides the integrated jitter RMS in different regions of the spectrum, i.e. 1H
1Hz to 2kHz and 1Hz to 100kHz. The values of jitter in the first region allow to evaluate
the jitter in the bandwidth of the SoftPLL with respect to the jitter over the entire
measurement bandwidth.
Additionally to frequency-domain analysis, Table~\ref{tab:adev} provides time-domain analysis.
Allan Deviation is measured by the Symmetricom 3120A Test Probe at each
of the three switches for different values of integration time with an
equivalent noise bandwidth (ENBW) of 50Hz. Both, Allan Deviation and the phase noise analysis
confirm an accumulation of phase noise in the lower frequencies of the spectrum.
\vspace{-0.4cm}
\begin{table}[!ht]
\centering
\scriptsize
......@@ -377,13 +385,7 @@ ext. PLL & 30Hz & SW 1 & 4.4ps & 4.8p
\end{tabular}
\caption{Integrated jitter RMS in different regions of the spectrum.}
\label{tab:phaseNoise}
\end{table}\vspace{-0.5cm}
Additionally to frequency-domain analysis, Table~\ref{tab:adev} provides time-domain analysis.
Allan Deviation is measured by the Symmetricom 3120A Test Probe at each
of the three switches for different values of integration time with an
equivalent noise bandwidth (ENBW) of 50Hz. Both, Allan Deviation and the phase noise analysis
confirm an accumulation of phase noise in the lower frequencies of the spectrum.
\end{table}\vspace{-0.7cm}
\begin{table}[!ht]
\centering
\scriptsize
......@@ -429,11 +431,12 @@ is minimized, which is shown in the measurement results.
The measurements discussed in section~\ref{sec:syncEchar} and depicted in
Fig.~\ref{fig:wanderTransfer1} agree closely with the transfer function estimated by our
model of the SoftPLL. We therefore consider the model valid and use it to predict the impact
of leaking of the phase noise from the VCO. The VCO phase noise transfer function estimated
from the model is depicted in Fig.~\ref{fig:slaveVCOLeaking} (red line).
of leaking of the phase noise from the VCO (VM53S3). The effect of the VCO phase noise, as
estimated from the model, is depicted in Fig.~\ref{fig:slaveVCOLeaking} (red line).
At the frequencies between 1Hz and 5Hz, the modelled VCO's leaking phase noise is comparable
with the phase noise of the GM reference (black line), increasing to the phase noise floor in
the spectrum of the WR Switch 1 phase noise (blue line).
\vspace{-0.5cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/slaveVCOLeaking.jpg}
......@@ -443,16 +446,16 @@ the spectrum of the WR Switch 1 phase noise (blue line).
In order to prevent the phase noise leaking, the SoftPLL was modified to provide
stronger rejection of the VCO phase noise. The modified SoftPLL has a bandwidth of 200Hz
with rejection characteristics depicted of -58dB@1Hz, -34dB@5Hz and -24db@10Hz (compared
with the VCO rejection characteristics depicted of -58dB@1Hz, -34dB@5Hz and -24db@10Hz (compared
with the characteristics of the current SoftPLL: -48dB@1Hz, -20dB@5Hz and -7db@10Hz).
% in Table~\ref{tab:VCOrejectionParams}.
The phase noise
of the WR Switch 1 with modified SoftPLL is depicted in Fig.~\ref{fig:slaveVCOLeaking} (green
line). The phase noise of the WR Switch 1 with modified SoftPLL does not exhibit any
phase noise accumulation. This improves the Allan Deviation, the new ADEV measurements are
phase noise accumulation in the 1Hz-10Hz range. This improves the Allan Deviation, the new ADEV measurements are
provided in Table~\ref{tab:adev}.
Theoretically, the larger bandwidth of the modified SoftPLL could lead to
jitter accumulation at higher frequencies due to a less aggressive filtering of the phase noise above 35Hz. However,
increased due to a less aggressive filtering of the phase noise above 35Hz. However,
measurement with a cascade of two WR Switches running the modified SoftPLL and connected to the GM show a decrease
of jitter compared to the non-modified SoftPLL, as presented in
Table~\ref{tab:phaseNoise}.
......@@ -517,7 +520,7 @@ the local oscillator.
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/improvedGM.jpg}
\caption{Phase noise.}
\label{fig:improvedGM}
\end{figure}\vspace{-0.4cm}
\end{figure}\vspace{-0.3cm}
The modification of the GM does not allow the GM to phase-align its \textit{local PTP clock signal}
with the PPS input. Therefore, it has limited usefulness. However, the ongoing design of
......@@ -566,29 +569,32 @@ lock even after the injection of wander was initiated.
The MTIE and TDEV of the switch running the modified SoftPLL are depicted in
Fig.~\ref{fig:SyncEcombo}-3 and Fig.~\ref{fig:SyncEcombo}-4 for the case when
the WR PTP is enabled and when it is disabled, thus the switch is only syntonized.
\vspace{-0.4cm}
In order to compare the frequency transfer using the currently available SoftPLL and the
SoftPLL modified to be SyncE compliant, phase noise was measured at WR~Switch~1 using the
setup depicted in Fig.~\ref{fig:phaseNoise-setup} (Symmetricom 3120A).
Fig.~\ref{fig:SyncE-compare} shows
that the unmodified SoftPLL (blue) has a very low integrated jitter of 4ps RMS (from 1Hz to 100kHz).
The SyncE-compliant SoftPLL (pink) has a much higher jitter in the 1-10Hz bandwidth that results
in a total integrated jitter of 100ps RMS. This is attributed to the the VCO (VM53S3)
that exhibits high phase noise in the 1-10Hz region when not controlled (red trace).
\vspace{-0.3cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{measurements/WRclockChar/SyncECompliantCcombo.jpg}
\caption{Characteristics of WR switch with SyncE-compliant SoftPLL.}
\label{fig:SyncEcombo}
\end{figure}\vspace{-0.3cm}
In order to compare the frequency transfer using the currently available SoftPLL and the
SoftPLL modified to be SyncE compliant, phase noise was measured at WR~Switch~1 using the
setup depicted in Fig.~\ref{fig:phaseNoise-setup} (Symmetricom 3120A). Fig.~\ref{fig:SyncE-compare} shows
that the unmodified SoftPLL (blue) has a very low integrated jitter of 4ps RMS (from 1Hz to 100kHz).
The SyncE-compliant SoftPLL (pink) has a much higher jitter in the 1-10Hz bandwidth that results
in a total integrated jitter of 100ps RMS. This is attributed to the the VCTCXO
that exhibits high phase noise in the 1-10Hz region when not controlled (red trace). An
An
oscillator with a better phase noise profile in that region (e.g. -70 dBc/Hz at 1Hz) can lower the
disparity of performance between the two version of the SoftPLL.
\vspace{-0.3cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/SyncE-compare.jpg}
\caption{Phase noise transfer.}
\label{fig:SyncE-compare}
\end{figure}
\end{figure}\vspace{-0.3cm}
\section{Conclusions}
\label{conclusions}
......
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