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including feedback from reviewers to ISPCS19`6 article

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papers/ISPCS2016/wrClockCharacteristics.bib
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......@@ -157,9 +157,9 @@
howpublished = {\\\url{http://www.ohwr.org/attachments/3833/WR-SyncE-characteristics-report.v3-2015-02-27.pdf}}
}
@electronic{syncEtest3,
title = "{SyncE Characteristics of a White Rabbit Switch}",
title = "{White Rabbit Switch performance in Grandmaster mode}",
author= "M.Rizzi",
howpublished = {}
howpublished = {\\\url{http://www.ohwr.org/documents/475}}
}
@Inproceedings{P1588-HA-enhancements,
author={O. Ronen and M. Lipinski},
......
papers/ISPCS2016/wrClockCharacteristics.tex
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......@@ -45,7 +45,7 @@
\and
\IEEEauthorblockN{Maciej Lipi\'{n}ski, Tomasz Wlostowski}
% \IEEEauthorblockN{Tomasz Wlostowski}
\IEEEauthorblockN{Javier Serrano}
\IEEEauthorblockN{Javier Serrano, Grzegorz Daniluk}
\IEEEauthorblockA{CERN, Geneva, Switzerland}
\and
\IEEEauthorblockN{Paolo Ferrari}
......@@ -54,7 +54,6 @@
}
\begin{document}
\maketitle
......@@ -69,14 +68,14 @@ allow the control of the Layer~1 (L1) syntonisation by the PTP protocol. This ar
focuses on the frequency transfer characteristics of the L1 syntonisation in WR.
We first explain the interaction between L1 syntonisation and PTP synchronisation
in a WR node and describe the architecture of its the Phase-Locked Loop.
in a WR node and describe the architecture of its the Phase-Locked Loop (PLL).
We then characterize the frequency transfer through a WR network in two ways: measuring
the characteristics of the WR switch according to the Synchronous Ethernet (SyncE) metrics defined in ITU-T G.8262, and
performing phase noise analysis. The results of the measurements allow us to propose
improvements that might be useful for different types of WR applications. Metrology
laboratories might be interested in the optimisations made to significantly reduce the
phase noise. On the other hand, the telecom industry might be interested in the modifications
that make the WR switch SyncE-compliant but slightly deteriorate its performance. Notably,
that make the WR switch SyncE-compliant but \textcolor{red}{slightly} deteriorate its performance. Notably,
the latter was achieved merely by modifying the software that implements the
WR PLL.
\end{abstract}
......@@ -92,14 +91,14 @@ and initially all WR applications concerned accelerators. The open nature of
the project and the fact that WR is based on widely-used standards, made it a preferred
solution in a much wider range of applications. All of these applications benefit from the
high synchronisation accuracy that is provided by the WR extensions to the Precision Time
Protocol (WR PTP)\cite{wrdraft} and its implementation.
Protocol (WR~PTP)\cite{wrdraft} and its implementation.
The protocol aspects of WR are studied by the P1588 Working Group \cite{P1588WG} and constitute the
basis for features and a profile that are likely to be included in the new revision of the
IEEE1588 standard. The protocol aspects are intended to support implementation-specific
mechanisms that provide the high accuracy.
There are two key elements that distinguish the implementation of WR PTP from other PTP
There are two key elements that distinguish the implementation of WR~PTP from other PTP
implementations
\begin{itemize}
\item Tight cooperation between the PTP synchronisation and the Layer 1 (L1) syntonisation,
......@@ -114,7 +113,8 @@ implementation of the L1~syntonisation in WR is characterised using Synchronous
metrics and
phase noise transfer analysis. These measurements allow to suggest a number of possible
modifications to optimize phase-noise and to achieve compliance with SyncE.
In both cases, the impact on the L1 syntonisation performance is measured.
In both cases, the impact on the L1 syntonisation \textcolor{red}{and PTP synchronisation}
performance is measured.
\vspace{-0.1cm}
\section{PTP synchronisation and L1 syntonisation in White Rabbit}
......@@ -139,7 +139,7 @@ the medium. %\vspace{-0.2cm}
Unlike in many PTP implementations, in WR the PTP synchronisation and the L1 syntonisation
are made to tightly cooperate. In particular, the local PTP time and the \textit{L1 tx/rx clock signals}
are congruent and coherent in the WR network \cite{P1588-HA-enhancements}. This is because
are congruent and coherent in the WR network~\cite{P1588-HA-enhancements}. This is because
each of the WR nodes implements the
\textit{clock model} depicted in Fig.~\ref{fig:clocks}.
Thus, on a link directly connecting two WR nodes A and B, the
......@@ -169,6 +169,7 @@ rather than manipulating the \textit{time counter} value. The WR PLL not only sy
\textit{L1 rx clock signal} but also maintains the desired phase offset between these two
clock signals, a value so-called \textit{setpoint}. The architecture of the WR PLL is
explained in the next section.
\textcolor{red}{?stuff required by reviewer 2?}
% \vspace{-0,4cm}
\section{WR Phase-Locked Loop}
......@@ -246,7 +247,7 @@ This PLL works by comparing the difference between subsequent phase-tags to the
"ideal" period of the \textit{DDMTD clock signal}.
The \textit{Main PLL} controls the \textit{local PTP clock signal} that is a copy of the
\textit{L1 rx clock signal}, phase shifted by a programmable \textit{setpoint} that is provided by the WR PTP.
\textit{L1 rx clock signal}, phase shifted by a programmable \textit{setpoint} that is provided by the WR~PTP.
The PLL works by comparing the phase-tags of the \textit{L1 rx clock signal}
to the phase-tags of the \textit{local PTP clock signal}, corrected for the \textit{setpoint}.
Any change of the \textit{setpoint} value is applied with an LSB-step increment.
......@@ -258,7 +259,7 @@ signals produced by the DDMTD have frequency of a 3.814kHz. Since each rising ed
clock signals is timestamped, the phase-tags are provided to the SoftPLL at the DDMTD frequency.
This is indeed the sample rate of the SoftPLL and so its Nyquist frequency is 1.9kHz. With the
current parameters of the SoftPLL, the resolution of its phase-tags is 0.977ps and
its bandwidth is 35Hz.
its bandwidth is \textcolor{red}{30}Hz.
The SoftPLL determines the characteristics of the frequency transfer through a WR switch. These
are characterised in the next section according to the ITU-T G.8262 guidelines.
......@@ -269,7 +270,8 @@ The characteristics of the frequency transfer through a WR switch are measured a
ITU-T G.8262 recommendation for a synchronous Ethernet equipment slave clock. Such a measurement
allows to compare the "WR clock" with the "SyncE clock". Table~\ref{tab:SyncEchar}
summarizes the results of tests that are described in a number of documents
\cite{syncEtest1}\cite{syncEtest2}\cite{syncEtest3} available on the WR web-pages
% \cite{syncEtest1}\cite{syncEtest2}\cite{syncEtest3}
available on the WR web-pages
dedicated to tests \cite{wrTests}.
\begin{table}[!ht]
\scriptsize
......@@ -404,10 +406,10 @@ controlled oscillator (VM53S3). Table~\ref{tab:phaseNoise}
\scriptsize
\begin{tabular}{|c | c | l | c | c | c |} \hline
\textbf{GM lock to} &\textbf{SoftPLL} & \textbf{Meas.} & \multicolumn{3}{|c|}{\textbf{RMS jitter}} \\ \cline{4-6}
\textbf{ext. ref.} &\textbf{BW} & \textbf{at} & \textbf{1Hz-10Hz} & \textbf{1Hz-2Hz} & \textbf{1Hz-100Hz} \\ \hhline{======}
\textbf{ext. ref.} &\textbf{BW} & \textbf{at} & \textbf{1Hz-10Hz} & \textbf{1Hz-2kHz} & \textbf{1Hz-100kHz} \\ \hhline{======}
& & GM & 4.7ps & 9.0ps & 9.1ps \\ \hhline{~=====} %\cline{2-6}
SoftPLL & 30Hz & SW 1 & 7.1ps & 11.0ps & 11.0ps \\ \cline{3-6}
(current) & (current) & SW 2 & 8.8ps & 14.0ps & 12.0ps \\ \hhline{~=====} %\cline{2-6}
(current) & (current) & SW 2 & 8.8ps & 14.0ps & 14.0ps \\ \hhline{~=====} %\cline{2-6}
& 200Hz & SW 1 & 5.0ps & 10.0ps & 10.0ps \\ \cline{3-6}
& (modified) & SW 2 & 5.1ps & 10.0ps & 10.0ps \\ \hhline{======}
& & GM & $<$0.1ps & 1.0ps & 5.9ps \\ \hhline{~=====} %\cline{2-6}
......@@ -451,7 +453,7 @@ ext. PLL &SW 2 & 2.9e-10 & 8.3e-11 & 1.3e-11 &
\label{tab:adev}
\end{table}%\vspace{-0.3cm}
provides time-domain analysis.
Allan Deviation is measured by the Symmetricom 3120A Test Probe at each
Allan Deviation is measured by the Microsemi 3120A Test Probe at each
of the three switches for different values of integration time with an
equivalent noise bandwidth (ENBW) of 50Hz. Both, Allan Deviation and phase noise analysis
confirm an accumulation of phase noise in the lower frequencies of the spectrum.
......@@ -470,8 +472,8 @@ to the external reference, and 2) the WR switches syntonizing to the GM. These i
are described in the following subsection.
\vspace{-0.1cm}
\subsection{VCO noise leaking}
The phase noise spectrum of the WR Switch between 1Hz-10Hz suggest a undesired phase noise
\label{VCOnoiseLeaking}
The phase noise spectrum of the WR Switch between 1Hz-10Hz suggest \textcolor{red}{an} undesired phase noise
accumulation. We use our simulation model to tune SoftPLL such that the phase noise accumulation
is minimized, which is shown in the measurement results.
......@@ -493,21 +495,31 @@ with the characteristics of the current SoftPLL: -48dB@1Hz, -20dB@5Hz and -7db@1
of the WR Switch 1 with modified SoftPLL is depicted in Fig.~\ref{fig:slaveVCOLeaking} (green
line). The phase noise of WR Switch 1 with modified SoftPLL does not exhibit any
phase noise accumulation in the 1Hz-10Hz range. This improves the Allan Deviation. The new ADEV measurements are
provided in Table~\ref{tab:adev}.
% \vspace{-0.3cm}
\begin{figure}[ht]
provided in Table~\ref{tab:adev}.
% \vspace{-0.2cm}
% \begin{figure}[ht]
% \centering
% \includegraphics[width=0.4\textwidth]{measurements/WRclockChar/slaveVCOLeaking.jpg}
% \caption{Phase noise.}
% \label{fig:slaveVCOLeaking}
% \end{figure}\vspace{-0.1cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/slaveVCOLeaking.jpg}
% \includegraphics[width=0.3\textwidth]{measurements/WRclockChar/improvedGM.jpg}
\includegraphics[width=0.5\textwidth]{measurements/WRclockChar/phase-nosie-combined.jpg}
\caption{Phase noise.}
\label{fig:phaseNoiseCombon}
\label{fig:improvedGM}
\label{fig:slaveVCOLeaking}
\end{figure}\vspace{-0.3cm}
\end{figure}%\vspace{-0.3cm}
Theoretically, the larger bandwidth of the modified SoftPLL could lead to
increased due to a less aggressive filtering of the phase noise above 35Hz. However,
increased jitter due to a less aggressive filtering of the phase noise above 35Hz. However,
measurement with a cascade of two WR Switches running the modified SoftPLL and connected to the GM show a decrease
of jitter compared to the non-modified SoftPLL, as presented in
Table~\ref{tab:phaseNoise}.
% \vspace{-0.2cm}
\subsection{Syntonisation of GM to the external 10MHz reference}
\label{GMmodifications}
The GM WR Switch locks to the external 10MHz reference using a SoftPLL that requires 62.5MHz
input signal, as depicted in Fig.~\ref{fig:WRPLL}. It is the clock conversion that
......@@ -563,12 +575,12 @@ phase noise accumulation. A controlled oscillator with at least 10dB better phas
the best noise profile since less bandwidth would be required to reject the noise coming from
the local oscillator.
% \vspace{-0.3cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/improvedGM.jpg}
\caption{Phase noise.}
\label{fig:improvedGM}
\end{figure}%\vspace{-0.3cm}
% \begin{figure}[!ht]
% \centering
% \includegraphics[width=0.3\textwidth]{measurements/WRclockChar/improvedGM.jpg}
% \caption{Phase noise.}
% \label{fig:improvedGM}
% \end{figure}%\vspace{-0.3cm}
The modification of the GM does not allow the GM to phase-align its \textit{local PTP clock signal}
with the PPS input. Therefore, it has limited usefulness. However, the ongoing design of
......@@ -615,7 +627,7 @@ Fig.~\ref{fig:SyncEcombo}-1.
% \vspace{-0.3cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{measurements/WRclockChar/SyncECompliantCcombo.jpg}
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/SyncECompliantCcombo.jpg}
\caption{Characteristics of WR switch with SyncE-compliant SoftPLL.}
\label{fig:SyncEcombo}
\end{figure}%\vspace{-0.3cm}
......@@ -630,7 +642,7 @@ signal phase when the wander noise injection finished (at second 17). The switch
lock even after the injection of wander was initiated.
The MTIE and TDEV of the switch running the modified SoftPLL are depicted in
Fig.~\ref{fig:SyncEcombo}-3 and Fig.~\ref{fig:SyncEcombo}-4 for the case when
the WR PTP is enabled and when it is disabled. In the latter case, the switch is only syntonised.
the WR~PTP is enabled and when it is disabled. In the latter case, the switch is only syntonised.
In order to compare the frequency transfer using the currently available SoftPLL and the
SoftPLL modified to be SyncE compliant, phase noise was measured at WR~Switch~1 using the
......@@ -638,12 +650,12 @@ setup depicted in Fig.~\ref{fig:phaseNoise} (Microsemi 3120A).
Fig.~\ref{fig:SyncE-compare} shows
\begin{figure}[!ht]
\centering
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/SyncE-compare.jpg}
\includegraphics[width=0.3\textwidth]{measurements/WRclockChar/SyncE-compare.jpg}
\caption{Phase noise transfer.}
\label{fig:SyncE-compare}
\end{figure}%\vspace{-0.5cm}
that the unmodified SoftPLL (blue) has a very low integrated jitter of 4ps RMS (from 1Hz to 100kHz).
The SyncE-compliant SoftPLL (pink) has a much higher jitter in the 1-10Hz bandwidth that results
that the unmodified SoftPLL (black) has a very low integrated jitter of 4ps RMS (from 1Hz to 100kHz).
The SyncE-compliant SoftPLL (blue) has a much higher jitter in the 1-10Hz bandwidth that results
in a total integrated jitter of 100ps RMS. This is attributed to the the VCO (VM53S3)
that exhibits high phase noise in the 1-10Hz region when not controlled (red trace).
An
......@@ -651,6 +663,44 @@ oscillator with a better phase noise profile in that region (e.g. -70 dBc/Hz at
disparity of performance between the two versions of the SoftPLL.
% \vspace{-0.5cm}
\section{PTP Synchronisation with the modifications}
\label{PTPSynchWithModification}
\textcolor{red}{The performance of the WR PTP synchronisation with the described modifications to the
L1 syntonisation is evaluated in a cascade of 10 WR switches, as depicted in Fig.~\ref{fig:cascade}.
% The switches are connected in a daisy chain using 1m fibers.
The time error between the 10MHz output of the first switch, the Grandmaster, and that of the other
switches is measured over 30min using a 10GS/s oscilloscope. For each version of the Grandmaster, i.e.
the release and the modified version, three measurements are performed,
one for each SoftPLL versions: \\
M1 -- the release version of SoftPLL; \\
M2 -- the SoftPLL with 200Hz bandwidth described in \ref{VCOnoiseLeaking}; \\
M3 -- the SoftPLL compliant with SyncE described in \ref{sec:improvementsSyncE}.\\
The same version of SoftPLL is used in all the 9 switches.}
\textcolor{red}{The modifications affect mostly jitter that is calculated as standard deviation of
the measured time error.
The modification of the Grandmaster alone improves jitter as it minimizes
the initial noise that is amplified by the cascaded SoftPLLs. Similarly, increased bandwidth
of the SoftPLL (M2) alone improves jitter as it reduces the amplification of the initial noise.
The best results are achieved when both modifications are applied, in such case the precision
after 9 hops is 11.6ps and the accuracy is below 100ps. }
\textcolor{red}{On the other hand, the SyncE-compliant version
of the SoftPLL shows increased jitter and is unable to keep synchronisation after 4 switches.
This is due to the poor phase noise performance below 10Hz of the VM53S3 oscillator, a better
oscillator would help to keep the synchronisation. Still, the measurement shows that the WR PTP synchronisation with the
SyncE-compliant SoftPLL allows sub-ns synchronisation in a chain of 2 switches.}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.45\textwidth]{measurements/WRclockChar/switchCascade.jpg}
\caption{Characteristics of WR switch with SyncE-compliant SoftPLL.}
\label{fig:cascade}
\end{figure}\vspace{-0.3cm}
\section{Conclusions}
\label{conclusions}
......
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