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62998fa6
Commit
62998fa6
authored
Jun 08, 2016
by
Maciej Lipinski
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ISPCS2016 - fine tunning
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phase-nosie-combined.jpg
figures/measurements/WRclockChar/phase-nosie-combined.jpg
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phaseNoise-setupAndTransfer.jpg
.../measurements/WRclockChar/phaseNoise-setupAndTransfer.jpg
+0
-0
dmpll_diagram-ML.pdf
figures/protocol/dmpll_diagram-ML.pdf
+0
-0
wrClockCharacteristics.tex
papers/ISPCS2016/wrClockCharacteristics.tex
+23
-24
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figures/measurements/WRclockChar/phase-nosie-combined.jpg
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papers/ISPCS2016/wrClockCharacteristics.tex
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...
...
@@ -227,7 +227,7 @@ to an input \textit{clock signal} that can be either:
\item
the
\textit
{
clock signal
}
coming from an external reference.
\end{itemize}
The outputs of the DDMTD are lower-frequency clock signals, as explained in
\ref
{
sec:ddmtd
}
.
The
\textcolor
{
red
}{
rising edges
}
of these signals are
The
rising edges
of these signals are
timestamped using a
\textit
{
time counter
}
incremented by the
\textit
{
DDMTD clock signal
}
. These timestamps,
called phase-tags, are fed into the software implementation of a Proportional-Integral (PI)
controller that runs in an embedded CPU
\cite
{
LM32
}
inside the FPGA. The controller steers
...
...
@@ -242,14 +242,14 @@ block diagram of the WR PLL, which actually consists of two PLLs: Helper and Mai
\label
{
fig:WRPLL
}
\end{figure}
%\vspace{-0.2cm}
The
\textit
{
Helper PLL
}
controls the
\textit
{
DDMTD clock signal
}
.
This PLL works by comparing each phase-tag with its expected value. This value is obtained
by adding the period of the
\textit
{
DDMTD clock signal
}
to the previous phase-tag.
%
The \textit{Helper PLL} controls the \textit{DDMTD clock signal}.
%
This PLL works by comparing each phase-tag with its expected value. This value is obtained
%
by adding the period of the \textit{DDMTD clock signal} to the previous phase-tag.
%
%
The \textit{Helper PLL} controls the \textit{DDMTD clock signal}.
%
This PLL works by comparing the difference between subsequent phase-tags to the
%
"ideal" period of the \textit{DDMTD clock signal}.
The
\textit
{
Helper PLL
}
controls the
\textit
{
DDMTD clock signal
}
.
This PLL works by comparing the difference between subsequent phase-tags to the
"ideal" period of the
\textit
{
DDMTD clock signal
}
.
The
\textit
{
Main PLL
}
controls the
\textit
{
local PTP clock signal
}
that is a copy of the
\textit
{
L1 rx clock signal
}
, phase shifted by a programmable
\textit
{
setpoint
}
that is provided by the WR~PTP.
...
...
@@ -273,11 +273,7 @@ are characterised in the next section according to the ITU-T G.8262 guidelines.
\label
{
sec:syncEchar
}
The characteristics of the frequency transfer through a WR switch are measured according to
ITU-T G.8262 recommendation for a synchronous Ethernet equipment slave clock. Such a measurement
allows to compare the "WR clock" with the "SyncE clock". Table~
\ref
{
tab:SyncEchar
}
summarizes the results of tests that are described in a number of documents
% \cite{syncEtest1}\cite{syncEtest2}\cite{syncEtest3}
available on the WR web-pages
dedicated to tests
\cite
{
wrTests
}
.
allows to compare the "WR clock" with the "SyncE clock". Table~
\ref
{
tab:SyncEchar
}
\begin{table}
[!ht]
\scriptsize
\begin{tabular}
{
|c | c | c | c | c |
}
\hline
...
...
@@ -300,6 +296,10 @@ Wander transfer & 10 & Failed & Fig.~\ref{fig:wanderTrans
\caption
{
WR clock characteristics according to ITU-T G.8262 metrics.
}
\label
{
tab:SyncEchar
}
\end{table}
%\vspace{-0.2cm}
summarizes the results of tests that are described in a number of documents
% \cite{syncEtest1}\cite{syncEtest2}\cite{syncEtest3}
available on the WR web-pages
dedicated to tests
\cite
{
wrTests
}
.
The table does not include tests of transient response and holdover (section 11 of ITU-T G.8262).
These features are not supported by the current release of the WR switch. Tests of solutions under
development can be found in
\cite
{
syncEtest2
}
.
...
...
@@ -335,7 +335,7 @@ The tests results in Table~\ref{tab:SyncEchar} show clearly that the currently a
Although the wander and jitter generation of the WR switch are orders of magnitude better
than required by ITU-T G.8262, the WR switch fails the tests of wander transfer as well as wander
and jitter tolerance. Fig.~
\ref
{
fig:wanderTransfer1
}
shows that the transfer function of the
WR switch has a bandwidth of
\textcolor
{
red
}{
35Hz
}
and a phase gain of 3.3dB at 16Hz while ITU-T G.8262
WR switch has a bandwidth of
30Hz
and a phase gain of 3.3dB at 16Hz while ITU-T G.8262
requires a gain smaller than 0.2dB and a bandwidth between 1Hz and 10Hz for EEC-Option~1, and 0.1Hz
for EEC-Option~2.
\begin{figure}
[!ht]
...
...
@@ -387,7 +387,7 @@ at the GM WR switch (GM), WR switch 1 (SW1) and WR switch 2 (SW2).
\begin{figure}
[!ht]
\centering
\includegraphics
[width=0.5\textwidth]
{
measurements/WRclockChar/phaseNoise-setupAndTransfer.jpg
}
\caption
{
Phase noise measurement setup and phase noise
transfer
.
}
\caption
{
Phase noise measurement setup and phase noise
plot
.
}
\label
{
fig:phaseNoise
}
\end{figure}
%\vspace{-0.3cm}
...
...
@@ -428,8 +428,6 @@ ext. PLL & 30Hz & SW 1 & 4.4ps & 4.8p
\end{table}
%\vspace{-0.3cm}
provides the integrated RMS jitter in different regions of the spectrum,
i.e. 1Hz to 10Hz, 1Hz to 2kHz and 1Hz to 100kHz.
\textcolor
{
red
}{
The spectrum starts at 1Hz since some of the WR applications
\cite
{
biblio:WR-LIST
}
require
low jitter at such low frequencies.
}
The values of jitter in the first region allow to evaluate
the jitter in the bandwidth of the SoftPLL with respect to the jitter over the entire
measurement bandwidth.
...
...
@@ -478,7 +476,7 @@ The measurements presented in the previous section indicate that the phase noise
of the frequency transfer in the WR network can be improved at 1) the GM syntonizing
to the external reference, and 2) the WR switches syntonizing to the GM. These improvements
are described in the following subsection.
\vspace
{
-0.1cm
}
%
\vspace{-0.1cm}
\subsection
{
VCO noise leaking
}
\label
{
VCOnoiseLeaking
}
The phase noise spectrum of the WR Switch between 1Hz-10Hz suggest an undesired phase noise
...
...
@@ -515,13 +513,13 @@ provided in Table~\ref{tab:adev}.
\centering
% \includegraphics[width=0.3\textwidth]{measurements/WRclockChar/improvedGM.jpg}
\includegraphics
[width=0.5\textwidth]
{
measurements/WRclockChar/phase-nosie-combined.jpg
}
\caption
{
Phase noise.
}
\caption
{
Phase noise
plots: (a) with modified SoftPLL; (b) with modified GM
.
}
\label
{
fig:phaseNoiseCombon
}
\label
{
fig:improvedGM
}
\label
{
fig:slaveVCOLeaking
}
\end{figure}
%\vspace{-0.3cm}
Theoretically, the larger bandwidth of the modified SoftPLL could lead to
increased jitter due to a less aggressive filtering of the phase noise above
\textcolor
{
red
}{
35Hz
}
. However,
increased jitter due to a less aggressive filtering of the phase noise above
30Hz
. However,
measurement with a cascade of two WR Switches running the modified SoftPLL and connected to the GM show a decrease
of jitter compared to the non-modified SoftPLL (current), as presented in
Table~
\ref
{
tab:phaseNoise
}
.
...
...
@@ -643,7 +641,7 @@ It meets the noise transfer (sec. 10 of G.8262)
requirement of below 0.2dB gain peaking and confirms that the bandwidth is within the range
specified for the EEC-option-1. Fig.~
\ref
{
fig:SyncEcombo
}
-2 shows that the WR switch
with the modified SoftPLL correctly transferred the wander noise defined in
section 9.1.1 of G.8262. The TIE was measured with respect to a CS4000 and
\textcolor
{
red
}{
its plot
}
shows
section 9.1.1 of G.8262. The TIE was measured with respect to a CS4000 and
its plot
shows
the injected wander reference signal (blue) and the signal recovered by the DUT (red).
The DUT tracked the reference signal without losing the lock and quickly followed the reference
signal phase when the wander noise injection finished (at second 17). The switch was able to
...
...
@@ -654,15 +652,16 @@ the WR~PTP is enabled and when it is disabled. In the latter case, the switch is
In order to compare the frequency transfer using the currently available SoftPLL and the
SoftPLL modified to be SyncE compliant, phase noise was measured at WR~Switch~1 using the
setup depicted in Fig.~
\ref
{
fig:phaseNoise
}
(Microsemi 3120A).
setup depicted in Fig.~
\ref
{
fig:phaseNoise
}
(Microsemi 3120A) where the GM is modified as explained
in
\ref
{
GMmodifications
}
.
Fig.~
\ref
{
fig:SyncE-compare
}
shows
\vspace
{
-0.2cm
}
\begin{figure}
[!ht]
\centering
\includegraphics
[width=0.3\textwidth]
{
measurements/WRclockChar/SyncE-compare.jpg
}
\caption
{
Phase noise
transfer
.
}
\includegraphics
[width=0.3
5
\textwidth]
{
measurements/WRclockChar/SyncE-compare.jpg
}
\caption
{
Phase noise
plot
.
}
\label
{
fig:SyncE-compare
}
\end{figure}
%\vspace{-0.5cm}
that the unmodified SoftPLL (black) has a very low integrated jitter of
4
ps RMS (from 1Hz to 100kHz).
that the unmodified SoftPLL (black) has a very low integrated jitter of
5
ps RMS (from 1Hz to 100kHz).
The SyncE-compliant SoftPLL (blue) has a much higher jitter in the 1-10Hz bandwidth that results
in a total integrated jitter of 100ps RMS. This is attributed to the the VCO (VM53S3)
that exhibits high phase noise in the 1-10Hz region when not controlled (red trace).
...
...
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