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ISPCS2016: included comments/corrections from Javier

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papers/ISPCS2016/wrClockCharacteristics.tex
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......@@ -6,6 +6,9 @@
\usepackage{color,array}
\usepackage{hhline}
\graphicspath{ {../../figures/} }
\usepackage{enumerate}
\setlength{\abovecaptionskip}{0pt}
\setlength{\belowcaptionskip}{0pt}
\title{White Rabbit clock characteristics }
......@@ -32,23 +35,23 @@
\begin{abstract}
%\boldmath
White Rabbit (WR) extends Precision Time Protocol (PTP) to provide synchronisation with
sub-nanosecond accuracy and sub-50 picoseconds precision. The protocol aspects of WR
White Rabbit (WR) extends the Precision Time Protocol (PTP) to provide synchronisation with
sub-nanosecond accuracy and sub-50 picoseconds precision. The protocol aspects of the WR
extension are currently studied and integrated into the upcoming revision of PTP.
In the context of this work, mechanisms are added to
allow the control of the Layer~1 (L1) syntonisation by the PTP protocol. This article
focuses on the frequency transfer characteristics of the L1 syntonisation in WR.
We first explain the interaction between L1 syntonisation and PTP synchronisation
in a WR node and describe architecture of its the Phase-Locked Loop.
in a WR node and describe the architecture of its the Phase-Locked Loop.
We then characterize the frequency transfer through a WR network in two ways: measuring
characteristics of the WR switch according to the Synchronous Ethernet (SyncE) metrics defined in ITU-T G.8262, and
the characteristics of the WR switch according to the Synchronous Ethernet (SyncE) metrics defined in ITU-T G.8262, and
performing phase noise analysis. The results of the measurements allow us to propose
improvements that might be useful for different types of WR applications. The metrology
improvements that might be useful for different types of WR applications. Metrology
laboratories might be interested in the optimisations made to significantly reduce the
phase noise. On the other hand, the telecom industry might be interested in the modifications
that make WR switch SyncE-compliant but slightly deteriorate its performance. Notably,
the latter was achieved merely by modifying the software (C-code) that implements the
that make the WR switch SyncE-compliant but slightly deteriorate its performance. Notably,
the latter was achieved merely by modifying the software that implements the
WR PLL.
\end{abstract}
......@@ -59,14 +62,14 @@ The White Rabbit (WR) project is a multilaboratory, multicompany, and multinatio
collaboration to develop a versatile solution for control and data acquisition systems
where sub-nanosecond synchronisation accuracy is required.
The project was started within an effort to renovate the CERN control and timing system,
and initially all WR's applications concerned accelerators. The open nature of
and initially all WR applications concerned accelerators. The open nature of
the project and the fact that WR is based on widely-used standards, made it a preferred
solution in a much wider range of applications. All of these applications benefit from the
high synchronisation accuracy that is provided by the WR extensions to the Precision Time
Protocol (WR PTP)\cite{wrdraft} and its implementation.
The protocol aspects of WR are studied by the P1588 Working Group \cite{P1588WG} and constitute the
basis for features and profile that are likely to be included in the new revision of the
basis for features and a profile that are likely to be included in the new revision of the
IEEE1588 standard. The protocol aspects are intended to support implementation-specific
mechanisms that provide the high accuracy.
......@@ -78,12 +81,12 @@ implementations
\end{itemize}
This article analyses the implementation and the performance of the L1 syntonisation
in WR and then studies their further improvements.
in WR and then studies possible further improvements.
It first explains the architecture and implementation of the Phase-Locked Loop (PLL) used in WR
and the cooperation between PTP synchronisation and L1 syntonisation. The current
implementation of the L1~syntonisation in WR is characterised using Synchronous Ethernet (SyncE)
metrics and
phase noise transfer analysis. This measurements allow to suggest a number of possible
phase noise transfer analysis. These measurements allow to suggest a number of possible
modifications to optimize phase-noise and to achieve compliance with SyncE.
In both cases, the impact on the L1 syntonisation performance is measured.
......@@ -91,14 +94,14 @@ In both cases, the impact on the L1 syntonisation performance is measured.
The relation between the PTP~synchronisation and the L1~syntonisation is described in this
article as the relation between \textit{local PTP clock}, \textit{L1 tx clock signal}
and \textit{L1 rx clock signal}, all depicted in Fig.~\ref{fig:clocks}.
article as the relation between the \textit{local PTP clock}, the \textit{L1 tx clock signal}
and the \textit{L1 rx clock signal}, all depicted in Fig.~\ref{fig:clocks}.
The \textit{local PTP clock} of a WR node provides the node's
local estimate of the time of the Grandmaster (GM) to which it is synchronized.
local estimate of the time of the Grandmaster (GM) to which it is synchronised.
This clock has a \textit{time counter} that is a digital time representation
incremented at each rising edge of the \textit{local PTP clock signal}.
The \textit{L1 rx clock signal} is recovered from the reception of data from
the medium while the \textit{L1 tx clock signal} is s used in the transmission of data over
the medium while the \textit{L1 tx clock signal} is used in the transmission of data over
the medium.
\begin{figure}[!ht]
\centering
......@@ -108,23 +111,23 @@ the medium.
\end{figure}\vspace{-0.2cm}
Unlike in many PTP implementations, in WR the PTP synchronisation and the L1 syntonisation
are made to tightly cooperate. In particular, the local PTP time and \textit{L1 tx/rx clock signals}
are made to tightly cooperate. In particular, the local PTP time and the \textit{L1 tx/rx clock signals}
are congruent and coherent in the WR network \cite{P1588-HA-enhancements}. This is because
each of the WR nodes implements the
\textit{clock model} depicted in Fig.~\ref{fig:clocks}.
Thus, on a link directly connecting two WR nodes A and B, the
\textit{L1 tx clock signal} transmitted by node A at its port in the master state is
syntonized to its \textit{local PTP clock}. The WR node B has its port in the slave state and
its \textit{local PTP clock} is syntonized to the
\textit{L1 rx clock signal} received from the node A. As a result,
syntonised to its \textit{local PTP clock}. WR node B has its port in the slave state and
its \textit{local PTP clock} is syntonised to the
\textit{L1 rx clock signal} received from node A. As a result,
the \textit{local PTP clocks} of both WR nodes are frequency-traceable to the same source, their
GM, without intervention of the PTP protocol. The PTP
measurement of link-delay and offset from the master is used only to adjust the value of the
\textit{time counter} and the phase of the \textit{local PTP clock} of the WR node B.
\textit{time counter} and the phase of the \textit{local PTP clock} of WR node B.
% The process of synchronizing a WR node B to a WR node A with is summarized as follows:
% \begin{enumerate}
% \item the \textit{local PTP clock} of the node B is syntonized to its \textit{L1 rx clock signal},
% \item the \textit{local PTP clock} of the node B is syntonised to its \textit{L1 rx clock signal},
% \item the link-delay and the offset from the master between A and B are measured,
% \item the value of the \textit{time counter} of node B is corrected,
% \item the offset from the master between A and B that is below the \textit{time counter}
......@@ -135,8 +138,8 @@ measurement of link-delay and offset from the master is used only to adjust the
% using PTP measurements.%, so-called \textit{phase tracking}.
% \end{enumerate}
The synchronisation in WR is maintained by adjusting the phase (phase-steering)
rather than manipulating the \textit{time counter} value. The WR PLL not only syntonizes the \textit{local PTP clock} to the recovered
\textit{L1 rx clock signal} but also maintains desired phase offset between these two
rather than manipulating the \textit{time counter} value. The WR PLL not only syntonises the \textit{local PTP clock} to the recovered
\textit{L1 rx clock signal} but also maintains the desired phase offset between these two
clock signals, a value so-called \textit{setpoint}. The architecture of the WR PLL is
explained in the next section.
......@@ -170,7 +173,7 @@ The sampling operation performed by the flip-flops is similar to analog mixing a
filtering. Thus, the output clock signals, $clk_{Aout}$ and $clk_{Bout}$, are of a frequency
that is proportional to the frequency of the input clock signals. The phase, expressed in radians,
between the input signals is equal to that between the output signals. Therefore,
the time-difference between the phases of the input and output clock signals is
the time-difference between the edges of the input and output clock signals is
proportional and can be expressed as follows:
\begin{equation}
\label{eq:fddmtd}
......@@ -183,13 +186,14 @@ input clocks. This technique is used in the WR PLL described in the next section
\subsection{DDMTD-based software WR PLL (SoftPLL)}
The architecture of the SoftPLL is depicted in Fig.~\ref{fig:WRPLL}.
It uses DDMTD implemented in Field Programmable Gate Array (FPGA) to compare the
It uses DDMTD implemented in a Field Programmable Gate Array (FPGA) to compare the
\textit{local PTP clock signal}
to an input \textit{clock signal} that can be either:
\begin{itemize}
\item the \textit{L1 rx clock signal} recovered at the slave port, or
\item the \textit{clock signal} coming from an external reference.
\end{itemize}
\vspace{-0.4cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{protocol/dmpll_diagram-ML.pdf}
......@@ -200,9 +204,9 @@ The outputs of the DDMTD are lower-frequency clock signals, as explained in \ref
The rising edges of these signals are
timestamped using a \textit{time counter} incremented by the \textit{DDMTD clock signal}. These timestamps,
called phase-tags, are fed into the software implementation of a Proportional-Integral (PI)
controller that runs in an embedded CPU \cite{LM32} inside FPGA. The controller steers
two Voltage-Controlled Crystal Oscillator (VCXO); FRETHE025 generates the \textit{DDMTD clock signal},
VM53S3 generates the \textit{local PTP clock signal}. Fig.~\ref{fig:WRPLL} depicts a simplified
controller that runs in an embedded CPU \cite{LM32} inside the FPGA. The controller steers
two Voltage-Controlled Crystal Oscillators (VCXO); FRETHE025 generates the \textit{DDMTD clock signal},
VM53S3 generates \textit{local PTP clock signal}. Fig.~\ref{fig:WRPLL} depicts a simplified
block diagram of the WR PLL, which actually consists of two PLLs: Helper and Main.
The \textit{Helper PLL} controls the \textit{DDMTD clock signal}.
......@@ -215,11 +219,12 @@ The PLL works by comparing the phase-tags of the \textit{L1 rx clock signal}
to the phase-tags of the \textit{local PTP clock signal}, corrected for the \textit{setpoint}.
Any change of the \textit{setpoint} value is applied with an LSB-step increment.
The WR nodes use 62.5MHz clock signal which determines a number of SoftPLL's characteristics. The SoftPLL that receives 62.5MHz input signal
produces a \textit{DDMTD clocks signal} of 62.496185 MHz. The down-converted clock
signals produced by the DDMTD have frequency of 3.814kHz. Since each rising edge of these
The WR nodes use a 62.5MHz clock signal which determines a number of characteristics of the SoftPLL.
The SoftPLL that receives a 62.5MHz input signal
produces a \textit{DDMTD clock signal} of 62.496185 MHz. The down-converted clock
signals produced by the DDMTD have frequency of a 3.814kHz. Since each rising edge of these
clock signals is timestamped, the phase-tags are provided to the SoftPLL at the DDMTD frequency.
This is indeed the sample rate of the SoftPLL and so its digital bandwidth is 1.9kHz. With the
This is indeed the sample rate of the SoftPLL and so its Nyquist frequency is 1.9kHz. With the
current parameters of the SoftPLL, the resolution of its phase-tags is 0.977ps and
its bandwidth is 35Hz.
......@@ -232,7 +237,7 @@ are characterised in the next section according to the ITU-T G.8262 guidelines.
The characteristics of the frequency transfer through a WR switch are measured according to
ITU-T G.8262 recommendation for a synchronous Ethernet equipment slave clock. Such a measurement
allows to compare the "WR clock" with the "SyncE clock". Table~\ref{tab:SyncEchar}
summarizes results of tests that are described in a number of documents
summarizes the results of tests that are described in a number of documents
\cite{syncEtest1}\cite{syncEtest2}\cite{syncEtest3} available on the WR web-pages
dedicated to tests \cite{wrTests}.
\begin{table}[!ht]
......@@ -261,31 +266,31 @@ The table does not include tests of transient response and holdover (section 11
These features are not supported by the current release of the WR switch. Tests of solutions under
development can be found in \cite{syncEtest2}.
The results in Table~\ref{tab:SyncEchar} were obtained using dedicated SyncE tester,
The results in Table~\ref{tab:SyncEchar} were obtained using a dedicated SyncE tester,
Calnex Paragon-X, and general-purpose measurement equipment. The measurement setups are depicted in
Fig.~\ref{fig:allSetups} and described below:
\begin{enumerate}
\item CS4000 Cesium Frequency Standard (Cs) is the external reference for Paragon-X.
The WR Switch, which is the device under test (DUT), is free-running. Paragon-X is syntonized
to the DUT over 1GbE fiber link.
\begin{enumerate}[1]
\item A CS4000 Cesium Frequency Standard (Cs) is the external reference for the Paragon-X.
The WR Switch, which is the device under test (DUT), is free-running. The Paragon-X is syntonised
to the DUT over a 1GbE fiber link.
\item Cs is the external reference for Paragon-X. The DUT is syntonized to Paragon-X over 1GbE fiber link
connected to port 2 (P2). Paragon-X is syntonized to DUT over 1GbE fiber link on port 1 (P1).
\item The CS4000 is the external reference for the Paragon-X. The DUT is syntonised to Paragon-X over 1GbE fiber link
connected to port 2 (P2). The Paragon-X is syntonised to the DUT over a 1GbE fiber link on port 1 (P1).
\item CS is the external referenc of the GM. The 10MHz output of the GM is used as the
external reference for the CNT-91 time interval counters (TIC). The DUT is syntonized to GM switch over
fiber link. The CNT-91 TIC is configured to take TIE measurement every 1ms, the acquired
\item The CS4000 is the external reference of the GM. The 10MHz output of the GM is used as the
external reference for the CNT-91 time interval counter (TIC). The DUT is syntonised to the GM switch over
a fiber link. The CNT-91 TIC is configured to take Time Interval Error (TIE) measurements every 1ms. The acquired
data is filtered above 10Hz.
\item Cs is the external reference for Agilent 33250A function generator and two CNT-91
\item The CS4000 is the external reference for an Agilent 33250A function generator and two CNT-91
TICs. A customized GM WR Switch is fed with a
phase-modulated 10MHz clock signal generated by the function generator. The GM is
modified such that it does not use SoftPLL to syntonized to the input 10MHz clock
signal. So, the GM switch uses directly the input signal to generate the
\textit{L1 tx clock signal}. The DUT is syntonized to the \textit{L1 tx clock signal}
of the GM switch over 1GbE fiber link. The two CNT-91 TICs are
modified such that it does not use the SoftPLL to syntonise to the input 10MHz clock
signal. So, the GM switch uses the input signal directly to generate the
\textit{L1 tx clock signal}. The DUT is syntonised to the \textit{L1 tx clock signal}
of the GM switch over a 1GbE fiber link. The two CNT-91 TICs are
configured to make Time Interval Error (TIE) measurements of the 10MHz outputs of the
GM and the DUT at 1kHz sampling rate.
GM and the DUT at a 1kHz sampling rate.
\end{enumerate}\vspace{-0.3cm}
\begin{figure}[!ht]
\centering
......@@ -298,8 +303,8 @@ The tests results in Table~\ref{tab:SyncEchar} show clearly that the currently a
Although the wander and jitter generation of the WR switch are orders of magnitude better
than required by ITU-T G.8262, the WR switch fails the tests of wander transfer as well as wander
and jitter tolerance. Fig.~\ref{fig:wanderTransfer1} shows that the transfer function of the
WR switch has bandwidth of 35Hz and a phase gain of 3.3dB at 16Hz while the ITU-T G.8262
requires gain smaller than 0.2dB and bandwidth 1-10Hz for EEC-Option~1, 0.1Hz
WR switch has a bandwidth of 35Hz and a phase gain of 3.3dB at 16Hz while ITU-T G.8262
requires a gain smaller than 0.2dB and a bandwidth between 1Hz and 10Hz for EEC-Option~1, and 0.1Hz
for EEC-Option~2.
\vspace{-0.2cm}
\begin{figure}[!ht]
......@@ -315,15 +320,15 @@ for EEC-Option~2.
\label{fig:wanderTransfer1}
\end{figure}\vspace{-0.2cm}
The reasons for the failures of the tests are investigated in section \ref{sec:improvementsSyncE}
which proposes modifications to SoftPLL that make WR switch compliant with SyncE. The section
The reasons for the failures of the tests are investigated in section \ref{sec:improvementsSyncE},
which proposes modifications to the SoftPLL that make the WR switch compliant with SyncE. The section
provides measurements of WR performance with the proposed changes.
The section that follows characterizes L1 syntonisation using phase noise analysis.
\section{Phase noise measurement of L1 syntonisation}
The phase noise of frequency transfer through WR network is measured to evaluate the
The phase noise of frequency transfer through a WR network is measured to evaluate the
current performance and identify potential improvements. The measurement is done
at each state of a linear daisy chain of 3 WR switches in a setup depicted in Fig.~\ref{fig:phaseNoise-setup}.
\begin{figure}[!ht]\vspace{-0.5cm}
......@@ -333,19 +338,20 @@ at each state of a linear daisy chain of 3 WR switches in a setup depicted in Fi
\label{fig:phaseNoise-setup}
\end{figure}\vspace{-0.3cm}
The measurement setup includes CS4000 Cesium Frequency Standard (Cs),
Symmetricom 3120A High-Performance Phase Noise Test Probe, and 3 WR switches.
Cs is the external reference for the GM WR switch and the
Symmetricom Test Probe. The Test Probe is connected to the output of each of
the WR switches. This output provides 10MHz clock signal derived from the 62.5MHz
\textit{local PTP clock signal} using AD9516 PLL to minimize additional phase noise.
This setup is used to measure phase noise of the of \textit{local PTP clock signal}
at the GM WR switch (GM), the WR switch 1 (SW1) and the WR switch 2 (SW2).
The measurement setup includes a CS4000 Cesium Frequency Standard,
Microsemi 3120A High-Performance Phase Noise Test Probe, and 3 WR switches.
The CS4000 is the external reference for the GM WR switch and the
Microsemi Test Probe. The Test Probe is connected to the output of each of
the WR switches. This output provides a 10MHz clock signal derived from the 62.5MHz
\textit{local PTP clock signal} using a AD9516 PLL to minimize additional phase noise.
This setup is used to measure the phase noise of the of \textit{local PTP clock signal}
at the GM WR switch (GM), WR switch 1 (SW1) and WR switch 2 (SW2).
Fig.~\ref{fig:noiseTransfer} depicts results of these three measurements.
Fig.~\ref{fig:noiseTransfer} shows the results of these three measurements.
% and indicates the
% estimated phase noise floor. The noise floor is the combined noise estimated by 3120A and the
% probe noise.
\vspace{-0.4cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/noiseTransfer.jpg}
......@@ -355,7 +361,7 @@ Fig.~\ref{fig:noiseTransfer} depicts results of these three measurements.
The effect of gain peaking is clearly visible in the graph. The increase of
phase noise in the 1Hz-10Hz region suggests possible phase noise leaking from the voltage
controlled oscillator (VM53S3). Table~\ref{tab:phaseNoise}
provides the integrated jitter RMS in different regions of the spectrum, i.e. 1Hz to 10Hz,
provides the integrated RMS jitter in different regions of the spectrum, i.e. 1Hz to 10Hz,
1Hz to 2kHz and 1Hz to 100kHz. The values of jitter in the first region allow to evaluate
the jitter in the bandwidth of the SoftPLL with respect to the jitter over the entire
measurement bandwidth.
......@@ -363,8 +369,11 @@ measurement bandwidth.
Additionally to frequency-domain analysis, Table~\ref{tab:adev} provides time-domain analysis.
Allan Deviation is measured by the Symmetricom 3120A Test Probe at each
of the three switches for different values of integration time with an
equivalent noise bandwidth (ENBW) of 50Hz. Both, Allan Deviation and the phase noise analysis
equivalent noise bandwidth (ENBW) of 50Hz. Both, Allan Deviation and phase noise analysis
confirm an accumulation of phase noise in the lower frequencies of the spectrum.
The source of the phase noise in the lower frequencies of the spectrum is analysed in the
next section and methods to improve the frequency transfer over WR network are proposed.
\vspace{-0.4cm}
\begin{table}[!ht]
\centering
......@@ -383,9 +392,9 @@ ext. PLL & 30Hz & SW 1 & 4.4ps & 4.8p
& 200 & SW 1 & 1.2ps & 3.2ps & 3.3ps \\ \cline{3-6}
& (modified) & SW 2 & 1.5ps & 4.4ps & 4.5ps \\ \hline
\end{tabular}
\caption{Integrated jitter RMS in different regions of the spectrum.}
\caption{Integrated RMS jitter in different regions of the spectrum.}
\label{tab:phaseNoise}
\end{table}\vspace{-0.7cm}
\end{table}\vspace{-0.6cm}
\begin{table}[!ht]
\centering
\scriptsize
......@@ -400,20 +409,19 @@ SoftPLL &SW 2 & 6.9e-10 & 2.1e-10 & 2.7e-11 &
(current)&\multicolumn{6}{|c|}{\color{gray} \textbf{Modified SoftPLL (BW: 200Hz)}} \\ \cline{2-7}
&SW 1 & 1.1e-9 & 1.4e-10 & 1.4e-11 & 1.4e-12 & 1.4e-13 \\ \cline{2-7}
&SW 2 & 1.1e-9 & 1.4e-10 & 1.4e-11 & 1.4e-12 & 1.5e-13 \\ \hhline{=======}
&GM & 1.2e-11 & 1.7e-12 & 4.1e-13 & 7.7e-14 & tbd \\ \hhline{~======}
&GM & 1.2e-11 & 1.7e-12 & 4.1e-13 & 7.7e-14 & - \\ \hhline{~======}
&\multicolumn{6}{|c|}{\color{gray}\textbf{Current release of SoftPLL (BW: 30Hz)}} \\ \cline{2-7}
&SW 1 & 2.1e-10 & 6.4e-11 & 1.3e-11 & 1.1e-12 & tbd \\ \cline{2-7}
ext. PLL &SW 2 & 2.9e-10 & 8.3e-11 & 1.3e-11 & 1.1e-12 & tbd \\ \cline{2-7}
&SW 1 & 2.1e-10 & 6.4e-11 & 1.3e-11 & 1.1e-12 & - \\ \cline{2-7}
ext. PLL &SW 2 & 2.9e-10 & 8.3e-11 & 1.3e-11 & 1.1e-12 & - \\ \cline{2-7}
(modified)&\multicolumn{6}{|c|}{\color{gray} \textbf{Modified SoftPLL (BW: 200Hz)}} \\ \cline{2-7}
&SW 1 & 1.9e-10 & 2.2e-11 & 3.3e-12 & 3.2e-13 & tbd \\ \cline{2-7}
&SW 2 & 3.6e-10 & 3.8e-11 & 5.1e-12 & 5.1e-13 & tbd \\ \hline
&SW 1 & 1.9e-10 & 2.2e-11 & 3.3e-12 & 3.2e-13 & - \\ \cline{2-7}
&SW 2 & 3.6e-10 & 3.8e-11 & 5.1e-12 & 5.1e-13 & - \\ \hline
\end{tabular}
\caption{Allan Deviation, equivalent noise bandwidth of 50Hz.}
\label{tab:adev}
\end{table}\vspace{-0.5cm}
\end{table}\vspace{-0.7cm}
The source of the phase noise in the lower frequencies of the spectrum is analysed in the
next section and methods to improve the frequency transfer over WR network are proposed.
\section{Improvement of the phase noise}
\label{sec:improvementsPhaseNoise}
......@@ -433,26 +441,26 @@ Fig.~\ref{fig:wanderTransfer1} agree closely with the transfer function estimate
model of the SoftPLL. We therefore consider the model valid and use it to predict the impact
of leaking of the phase noise from the VCO (VM53S3). The effect of the VCO phase noise, as
estimated from the model, is depicted in Fig.~\ref{fig:slaveVCOLeaking} (red line).
At the frequencies between 1Hz and 5Hz, the modelled VCO's leaking phase noise is comparable
with the phase noise of the GM reference (black line), increasing to the phase noise floor in
the spectrum of the WR Switch 1 phase noise (blue line).
\vspace{-0.5cm}
At frequencies between 1Hz and 5Hz, the modelled VCO's leaking phase noise is comparable
with the phase noise of the GM reference (black line). The modelled noise increases to the
phase noise floor in the spectrum of the WR Switch 1 phase noise (blue line).
In order to prevent the phase noise leaking, the SoftPLL was modified to provide
stronger rejection of the VCO phase noise. The modified SoftPLL has a bandwidth of 200Hz
with the VCO rejection characteristics of -58dB@1Hz, -34dB@5Hz and -24db@10Hz (compared
with the characteristics of the current SoftPLL: -48dB@1Hz, -20dB@5Hz and -7db@10Hz).
\vspace{-0.3cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/slaveVCOLeaking.jpg}
\caption{Phase noise.}
\label{fig:slaveVCOLeaking}
\end{figure}\vspace{-0.3cm}
In order to prevent the phase noise leaking, the SoftPLL was modified to provide
stronger rejection of the VCO phase noise. The modified SoftPLL has a bandwidth of 200Hz
with the VCO rejection characteristics depicted of -58dB@1Hz, -34dB@5Hz and -24db@10Hz (compared
with the characteristics of the current SoftPLL: -48dB@1Hz, -20dB@5Hz and -7db@10Hz).
% in Table~\ref{tab:VCOrejectionParams}.
The phase noise
of the WR Switch 1 with modified SoftPLL is depicted in Fig.~\ref{fig:slaveVCOLeaking} (green
line). The phase noise of the WR Switch 1 with modified SoftPLL does not exhibit any
phase noise accumulation in the 1Hz-10Hz range. This improves the Allan Deviation, the new ADEV measurements are
line). The phase noise of WR Switch 1 with modified SoftPLL does not exhibit any
phase noise accumulation in the 1Hz-10Hz range. This improves the Allan Deviation. The new ADEV measurements are
provided in Table~\ref{tab:adev}.
Theoretically, the larger bandwidth of the modified SoftPLL could lead to
increased due to a less aggressive filtering of the phase noise above 35Hz. However,
......@@ -462,44 +470,44 @@ Table~\ref{tab:phaseNoise}.
\subsection{Syntonisation of GM to the external 10MHz reference}
The GM WR Switch locks to the external 10MHz reference using SoftPLL that requires 62.5MHz
The GM WR Switch locks to the external 10MHz reference using a SoftPLL that requires 62.5MHz
input signal, as depicted in Fig.~\ref{fig:WRPLL}. It is the clock conversion that
introduces undesired phase noise and needs to be optimized to improve performance of the
frequency transfer in the WR network.
The SoftPLL operates with 62.5MHz frequency because its usual input clock signal is a divided
125Mhz clock from a Gigabit Transceiver. In GM, however, SoftPLL is used
to lock to the external 10MHz reference. To provide SoftPLL with the required clock signal,
the 10MHz input is multiplied using an internal PLL of the FPGA, called Mixed
The SoftPLL operates with a 62.5MHz frequency because its usual input clock signal is a divided
125MHz clock from a Gigabit Transceiver. In the GM, however, the SoftPLL is used
to lock to the external 10MHz reference. To provide the SoftPLL with the required clock signal,
the 10MHz input is multiplied using an internal PLL of the FPGA, called a Mixed
Mode Clock Manager (MMCM). The phase noise spectrum of the 62.5MHz output
of the MMCM is measured with Agilent E5052B Phase Noise Analyser. It shows a large phase
noise power located between 10kHz and 2MHz, with a jitter RMS (integrated from 10kHz to 2MHz)
of the MMCM is measured with an Agilent E5052B Phase Noise Analyser. It shows a large phase
noise power located between 10kHz and 2MHz, with an RMS jitter (integrated from 10kHz to 2MHz)
of 155ps. This high frequency phase noise would be filtered out by an analogue PLL.
However, the SoftPLL cannot filter such noise because of its digital nature (Nyquist bandwidth
of 1.9kHz) and the digital nature of the DDMTD. The analogue equivalent of
the DDMTD has a low pass filter after the mixer to limit the bandwidth of the measurement
system. The DDMTD has no analogue components, instead the input phase noise is
filtered by the bandwidth of the D-type flip-flops (hundreds MHz) and by the filtering action of
system. The DDMTD has no analogue components. Instead the input phase noise is
filtered by the bandwidth of the D-type flip-flops (hundreds of MHz) and by the filtering action of
the deglitching algorithm \cite{tom}. Consequently, the remaining phase noise is
aliased over the Nyquist bandwidth of the SoftPLL acting as a white noise. This effect
aliased over the Nyquist bandwidth of the SoftPLL acting as white noise. This effect
can be seen in Fig.~\ref{fig:noiseTransfer}.
The Allan Deviation slope of the GM, see Table~\ref{tab:adev}, is the inverse of the
integration time which indicates White PM or Flicker PM noise. This is a confirmation of the
aliased white noise in the SoftPLL bandwidth.
In order to verify that the MMCM is indeed the problem and to measure the improvement
of using external PLL, the available on board AD9516 PLL is used to directly multiply the external
10MHz input reference. The the SoftPLL is bypassed and the multiplied clock signal is used
of using an external PLL, the available on board AD9516 PLL is used to directly multiply the external
10MHz input reference. The SoftPLL is bypassed and the multiplied clock signal is used
as the \textit{local PTP clock signal}. This solution allows to verify our suspicions with
minimal changes to the hardware.
Fig.~\ref{fig:improvedGM} provides the results of phase noise measured at the modified GM and
at the WR Switch 1 using either the current release of SoftPLL (BW: 30Hz) or its modified version
at WR Switch 1 using either the current release of SoftPLL (BW: 30Hz) or its modified version
(BW: 200Hz). The results confirm that the modified GM has a better phase noise profile in the lower
frequencies. This is also confirmed by the values of jitter RMS in Table~\ref{tab:phaseNoise}.
The downside of the GM's modification are the spurs that are especially visible above 1kHz.
They degrades the integrated jitter over the entire bandwidth to 5.9ps RMS. The spurs that
occur on the GM are partially filtered by the SoftPLL's noise transfer function of the
frequencies. This is also confirmed by the values of RMS jitter in Table~\ref{tab:phaseNoise}.
The downside of the GM modification are the spurs that are especially visible above 1kHz.
They degrade the integrated jitter over the entire bandwidth to 5.9ps RMS. The spurs that
occur on the GM are partially filtered by the SoftPLL noise transfer function of
WR Switch 1.
The origin of the spurs is likely to be related to suboptimal power supply decoupling and
noise coupling to the controlled oscillators.
......@@ -507,7 +515,7 @@ noise coupling to the controlled oscillators.
Table~\ref{tab:adev} provides measurement values of the Allan Deviation with the modified GM
and with two WR Switches using either the current or the modified SoftPLL. The modification
of the GM does not improve significantly the Allan Deviation results for the current SoftPLL,
as expected. However, the modified SoftPLL benefit from the lower phase noise of the GM with a
as expected. However, the modified SoftPLL benefits from the lower phase noise of the GM with a
significant reduction of ADEV.
The drawback of the modified SoftPLL is a worse phase noise in the 100Hz-1kHz region due to
......@@ -524,55 +532,55 @@ the local oscillator.
The modification of the GM does not allow the GM to phase-align its \textit{local PTP clock signal}
with the PPS input. Therefore, it has limited usefulness. However, the ongoing design of
new WR switch hardware will likely include dedicated external PLL to lock to the external reference.
new WR switch hardware will likely include a dedicated external PLL to lock to the external reference.
\section{SyncE-compliance}
\label{sec:improvementsSyncE}
Compliance of L1 syntonisation in WR with SyncE specifications (ITU-T G.8262) might be helpful
in future adaptation of the WR-based features integrated into the new revision of PTP.
in a future adaptation of the WR-based features integrated into the new revision of PTP.
This section proves that WR can be made SyncE-compliant only through software changes in the
SoftPLL.
The SoftPLL fails to pass the wander tolerance tests by unlocking when the modulating
frequency reaches 1Hz and the time amplitude reaches 250ns. Increasing the de-locking
threshold is not a solution since the wander frequency might drive the
local oscillator (VM53S3) out of it's range, e.g. for 10Hz modulating frequency, the
local oscillator (VM53S3) out of it's range.
In order to meet the SyncE characteristics without changing the hardware, the SoftPLL's
In order to meet the SyncE characteristics without changing the hardware, the SoftPLL
software was modified as follows:
\begin{enumerate}
\item \textbf{The bandwidth was reduced to 5Hz}. This allows to the meet SyncE EEC-Option 1
\item \textbf{The bandwidth was reduced to 5Hz}. This allows to the meet the SyncE EEC-Option 1
specification and filter the low frequency wander noise that can drive the
oscillator outside its pull-range.
\item \textbf{Multiple Unit Interval (UI) tracking of error was implemented.} This
allows the SoftPLL to track errors greater than $\pm$16ns.
\item \textbf{Locking logic was modified to allow tracking of large zero-mean wander.}
The default locking logic detects out-of-lock situation if the error signal is outside a
The default locking logic detects an out-of-lock situation if the error signal is outside a
threshold for a predetermined amount of time. This logic cannot work with large
wander errors since it would require threshold equal to the
wander errors since it would require a threshold equal to the
wander amplitude. The modified locking logic implements out-of-lock detection
based on averaged error, with 3-second moving window.
based on averaged error, with a 3-second moving window.
\end{enumerate}
The following 3 tests from subsection~\ref{sec:syncEchar} were repeated using the modified
The 3 tests from subsection~\ref{sec:syncEchar} were repeated using the modified
SoftPLL: wander tolerance (op-1 only), jitter tolerance, and wander transfer. All tests
were successfully passed. The transfer function of the modified SoftPLL is depicted in
Fig.~\ref{fig:SyncEcombo}-1. It meets the noise transfer (sec. 10 of G.8262)
requirement of below 0.2dB gain peaking and confirms that the bandwidth is within the range
specified for the EEC-option-1. Fig.~\ref{fig:SyncEcombo}-2 shows that the WR switch
with the modified SoftPLL correctly transferred the wander noise defined in
section 9.1.1 of G.8262. The TIE was measured with respect to Cs and shows
the injected wander reference signal (blue) and the signal recovered by DUT (red).
The DUT tracked the reference signal without losing the lock and quickly follow the reference
section 9.1.1 of G.8262. The TIE was measured with respect to a CS4000 and shows
the injected wander reference signal (blue) and the signal recovered by the DUT (red).
The DUT tracked the reference signal without losing the lock and quickly followed the reference
signal phase when the wander noise injection finished (at second 17). The switch was able to
lock even after the injection of wander was initiated.
The MTIE and TDEV of the switch running the modified SoftPLL are depicted in
Fig.~\ref{fig:SyncEcombo}-3 and Fig.~\ref{fig:SyncEcombo}-4 for the case when
the WR PTP is enabled and when it is disabled, thus the switch is only syntonized.
the WR PTP is enabled and when it is disabled. In the latter case, the switch is only syntonised.
In order to compare the frequency transfer using the currently available SoftPLL and the
SoftPLL modified to be SyncE compliant, phase noise was measured at WR~Switch~1 using the
setup depicted in Fig.~\ref{fig:phaseNoise-setup} (Symmetricom 3120A).
setup depicted in Fig.~\ref{fig:phaseNoise-setup} (Microsemi 3120A).
Fig.~\ref{fig:SyncE-compare} shows
that the unmodified SoftPLL (blue) has a very low integrated jitter of 4ps RMS (from 1Hz to 100kHz).
The SyncE-compliant SoftPLL (pink) has a much higher jitter in the 1-10Hz bandwidth that results
......@@ -587,14 +595,14 @@ that exhibits high phase noise in the 1-10Hz region when not controlled (red tra
\end{figure}\vspace{-0.3cm}
An
oscillator with a better phase noise profile in that region (e.g. -70 dBc/Hz at 1Hz) can lower the
disparity of performance between the two version of the SoftPLL.
\vspace{-0.3cm}
disparity of performance between the two versions of the SoftPLL.
\vspace{-0.4cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/SyncE-compare.jpg}
\caption{Phase noise transfer.}
\label{fig:SyncE-compare}
\end{figure}\vspace{-0.3cm}
\end{figure}\vspace{-0.9cm}
\section{Conclusions}
\label{conclusions}
......@@ -607,9 +615,9 @@ with timing characteristics of a synchronous Ethernet equipment slave
clock was achieved this way. On the other hand, hardware modification is desired to
improve the phase noise profile of WR.
The increasing number of WR's applications pushes the limits of its performance while
The increasing number of WR applications pushes the limits of its performance while
the standardisation makes it likely to be used in less stringent applications that require
compatibility with legacy equipment. We have shown that adaptation in different direction is
compatibility with legacy equipment. We have shown that adaptation in different directions is
feasible, straightforward and often requires only software modifications.
......
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