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ISPCS2016 article - fine tuning

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papers/ISPCS2016/wrClockCharacteristics.bib
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......@@ -50,9 +50,6 @@
@Misc{wrdraft,
author = "E.G. Cota and M. Lipi\'{n}ski and T. W\l{}ostowski and E.V.D. Bij and J. Serrano",
title = "{White Rabbit Specification: Draft for Comments}",
note = "v2.0",
month = "july",
year = "2011",
howpublished = {\url{www.ohwr.org/documents/21}}
}
......@@ -62,7 +59,7 @@
month = "may",
year = "2011",
school = "Warsaw University of Technology",
howpublished = {\url{http://www.ohwr.org/documents/80}}
howpublished = {\url{www.ohwr.org/documents/80}}
}
@Inproceedings{wrproject,
......@@ -77,14 +74,14 @@
@article{ddmtd,
author = "P. Moreira and P. Alvarez and J. Serrano and I. Darwezeh and T. Wlostowski",
title = "{Digital Dual Mixer Time Difference for Sub-Nanosecond Time Synchronization in Ethernet}",
journal = "Frequency Control Symposium (FCS), 2010 IEEE International",
journal = "FCS 2010 IEEE International",
address = "London, UK",
year = "2010",
}
@electronic{ppsimanual,
title = "{PPSi Manual}",
howpublished = {\\\url{www.ohwr.org/attachments/download/1952/ppsi-manual-130311.pdf}}
howpublished = {\url{www.ohwr.org/attachments/download/1952/ppsi-manual-130311.pdf}}
}
@electronic{ptpd,
......@@ -104,7 +101,7 @@
@electronic{gladstone,
title = "{White Rabbit Developers Mailing List}",
howpublished = {\\\url{lists.ohwr.org/sympa/arc/white-rabbit-dev/2014-03/msg00015.html}}
howpublished = {\url{lists.ohwr.org/sympa/arc/white-rabbit-dev/2014-03/msg00015.html}}
}
@electronic{spec,
......@@ -167,10 +164,16 @@ booktitle={2015 IEEE International Symposium on Precision Clock Synchronization
title={Enhanced synchronization accuracy in IEEE1588},
}
@electronic{wrTests,
title = "{White Rabbit Test Reports}",
howpublished = {\\\url{http://www.ohwr.org/projects/wr-switch-testing/wiki}}
title = "{WR Test Reports}",
howpublished = {\url{www.ohwr.org/projects/wr-switch-testing/wiki}}
}
@electronic{LM32,
title = "{LatticeMico32 Open}",
howpublished = {\\\url{http://www.ohwr.org/projects/lm32}}
howpublished = {\url{http://www.ohwr.org/projects/lm32}}
}
@article{biblio:WR-LIST,
author = "T. Wlostowski and J. Serrano and G. Daniluk and M. Lipinski and F. Vaga",
title = "{Trigger and RF distribution using White Rabbit}",
journal = "{Proceedings of ICALEPCS2015}",
}
\ No newline at end of file
papers/ISPCS2016/wrClockCharacteristics.tex
View file @ be285fe3
......@@ -63,19 +63,19 @@
White Rabbit (WR) extends the Precision Time Protocol (PTP) to provide synchronisation with
sub-nanosecond accuracy and sub-50 picoseconds precision. The protocol aspects of the WR
extension are currently studied and integrated into the upcoming revision of PTP.
In the context of this work, mechanisms are added to
In the context of this PTP revision, mechanisms are added to
allow the control of the Layer~1 (L1) syntonisation by the PTP protocol. This article
focuses on the frequency transfer characteristics of the L1 syntonisation in WR.
We first explain the interaction between L1 syntonisation and PTP synchronisation
in a WR node and describe the architecture of its the Phase-Locked Loop (PLL).
in a WR device and describe the architecture of its Phase-Locked Loop (PLL).
We then characterize the frequency transfer through a WR network in two ways: measuring
the characteristics of the WR switch according to the Synchronous Ethernet (SyncE) metrics defined in ITU-T G.8262, and
performing phase noise analysis. The results of the measurements allow us to propose
improvements that might be useful for different types of WR applications. Metrology
laboratories might be interested in the optimisations made to significantly reduce the
phase noise. On the other hand, the telecom industry might be interested in the modifications
that make the WR switch SyncE-compliant but \textcolor{red}{slightly} deteriorate its performance. Notably,
that make the WR switch SyncE-compliant but deteriorate its performance. Notably,
the latter was achieved merely by modifying the software that implements the
WR PLL.
\end{abstract}
......@@ -91,7 +91,7 @@ and initially all WR applications concerned accelerators. The open nature of
the project and the fact that WR is based on widely-used standards, made it a preferred
solution in a much wider range of applications. All of these applications benefit from the
high synchronisation accuracy that is provided by the WR extensions to the Precision Time
Protocol (WR~PTP)\cite{wrdraft} and its implementation.
Protocol (WR~PTP)~\cite{wrdraft} and its implementation.
The protocol aspects of WR are studied by the P1588 Working Group \cite{P1588WG} and constitute the
basis for features and a profile that are likely to be included in the new revision of the
......@@ -99,22 +99,22 @@ IEEE1588 standard. The protocol aspects are intended to support implementation-s
mechanisms that provide the high accuracy.
There are two key elements that distinguish the implementation of WR~PTP from other PTP
implementations
implementations:
\begin{itemize}
\item Tight cooperation between the PTP synchronisation and the Layer 1 (L1) syntonisation,
\item Enhanced timestamping precision using phase detection.
\item tight cooperation between the PTP synchronisation and the Layer 1 (L1) syntonisation, and
\item enhanced timestamping precision using phase detection.
\end{itemize}
This article analyses the implementation and the performance of the L1 syntonisation
in WR and then studies possible further improvements.
in WR and then studies its possible further improvements.
It first explains the architecture and implementation of the Phase-Locked Loop (PLL) used in WR
and the cooperation between PTP synchronisation and L1 syntonisation. The current
implementation of the L1~syntonisation in WR is characterised using Synchronous Ethernet (SyncE)
metrics and
phase noise transfer analysis. These measurements allow to suggest a number of possible
modifications to optimize phase-noise and to achieve compliance with SyncE.
In both cases, the impact on the L1 syntonisation \textcolor{red}{and PTP synchronisation}
performance is measured.
In both cases, the impact on the L1 syntonisation and PTP synchronisation
performance is evaluated.
\vspace{-0.1cm}
\section{PTP synchronisation and L1 syntonisation in White Rabbit}
......@@ -132,7 +132,7 @@ the medium while the \textit{L1 tx clock signal} is used in the transmission of
the medium. %\vspace{-0.2cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.45\textwidth]{p1588/1588-ha-L1vsPTP.jpg}
\includegraphics[width=0.5\textwidth]{p1588/1588-ha-L1vsPTP.jpg}
\caption{L1 and PTP clock signals.}
\label{fig:clocks}
\end{figure}%\vspace{-0.3cm}
......@@ -141,7 +141,7 @@ Unlike in many PTP implementations, in WR the PTP synchronisation and the L1 syn
are made to tightly cooperate. In particular, the local PTP time and the \textit{L1 tx/rx clock signals}
are congruent and coherent in the WR network~\cite{P1588-HA-enhancements}. This is because
each of the WR nodes implements the
\textit{clock model} depicted in Fig.~\ref{fig:clocks}.
\textit{WR PTP clock model} depicted in Fig.~\ref{fig:clocks}.
Thus, on a link directly connecting two WR nodes A and B, the
\textit{L1 tx clock signal} transmitted by node A at its port in the master state is
syntonised to its \textit{local PTP clock}. WR node B has its port in the slave state and
......@@ -169,7 +169,7 @@ rather than manipulating the \textit{time counter} value. The WR PLL not only sy
\textit{L1 rx clock signal} but also maintains the desired phase offset between these two
clock signals, a value so-called \textit{setpoint}. The architecture of the WR PLL is
explained in the next section.
\textcolor{red}{?stuff required by reviewer 2?}
% \textcolor{red}{?stuff required by reviewer 2?}
% \vspace{-0,4cm}
\section{WR Phase-Locked Loop}
......@@ -184,7 +184,7 @@ The DDMTD uses digital mixing to produce output clock signals of lower frequency
the input clock signals. The operation of DDMTD is explained in Fig.~\ref{fig:ddmtd}.
The input clock signals are sampled with D-type flip-flops that are clocked with an offset
clock signal, $clk_{DDMTD}$,
generated from one of the inputs.% \vspace{-0.2cm}
generated from one of the inputs. % \vspace{-0.2cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{p1588/1588-ha-dmtd.jpg}
......@@ -227,14 +227,14 @@ to an input \textit{clock signal} that can be either:
\item the \textit{clock signal} coming from an external reference.
\end{itemize}
The outputs of the DDMTD are lower-frequency clock signals, as explained in \ref{sec:ddmtd}.
The rising edges of these signals are
The \textcolor{red}{rising edges} of these signals are
timestamped using a \textit{time counter} incremented by the \textit{DDMTD clock signal}. These timestamps,
called phase-tags, are fed into the software implementation of a Proportional-Integral (PI)
controller that runs in an embedded CPU \cite{LM32} inside the FPGA. The controller steers
two Voltage-Controlled Crystal Oscillators (VCXO); FRETHE025 generates the \textit{DDMTD clock signal},
VM53S3 generates \textit{local PTP clock signal}. Fig.~\ref{fig:WRPLL} depicts a simplified
block diagram of the WR PLL, which actually consists of two PLLs: Helper and Main.
% \vspace{-0.4cm}
% \vspace{-0.1cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{protocol/dmpll_diagram-ML.pdf}
......@@ -243,8 +243,13 @@ block diagram of the WR PLL, which actually consists of two PLLs: Helper and Mai
\end{figure}%\vspace{-0.2cm}
The \textit{Helper PLL} controls the \textit{DDMTD clock signal}.
This PLL works by comparing the difference between subsequent phase-tags to the
"ideal" period of the \textit{DDMTD clock signal}.
This PLL works by comparing each phase-tag with its expected value. This value is obtained
by adding the period of the \textit{DDMTD clock signal} to the previous phase-tag.
%
% The \textit{Helper PLL} controls the \textit{DDMTD clock signal}.
% This PLL works by comparing the difference between subsequent phase-tags to the
% "ideal" period of the \textit{DDMTD clock signal}.
The \textit{Main PLL} controls the \textit{local PTP clock signal} that is a copy of the
\textit{L1 rx clock signal}, phase shifted by a programmable \textit{setpoint} that is provided by the WR~PTP.
......@@ -252,14 +257,14 @@ The PLL works by comparing the phase-tags of the \textit{L1 rx clock signal}
to the phase-tags of the \textit{local PTP clock signal}, corrected for the \textit{setpoint}.
Any change of the \textit{setpoint} value is applied with an LSB-step increment.
The WR nodes use a 62.5MHz clock signal which determines a number of characteristics of the SoftPLL.
The WR switches use a 62.5MHz clock signal which determines a number of characteristics of the SoftPLL.
The SoftPLL that receives a 62.5MHz input signal
produces a \textit{DDMTD clock signal} of 62.496185 MHz. The down-converted clock
signals produced by the DDMTD have frequency of a 3.814kHz. Since each rising edge of these
clock signals is timestamped, the phase-tags are provided to the SoftPLL at the DDMTD frequency.
This is indeed the sample rate of the SoftPLL and so its Nyquist frequency is 1.9kHz. With the
current parameters of the SoftPLL, the resolution of its phase-tags is 0.977ps and
its bandwidth is \textcolor{red}{30}Hz.
its bandwidth is 30Hz.
The SoftPLL determines the characteristics of the frequency transfer through a WR switch. These
are characterised in the next section according to the ITU-T G.8262 guidelines.
......@@ -268,7 +273,7 @@ are characterised in the next section according to the ITU-T G.8262 guidelines.
\label{sec:syncEchar}
The characteristics of the frequency transfer through a WR switch are measured according to
ITU-T G.8262 recommendation for a synchronous Ethernet equipment slave clock. Such a measurement
allows to compare the "WR clock" with the "SyncE clock". Table~\ref{tab:SyncEchar}
allows to compare the "WR clock" with the "SyncE clock". Table~\ref{tab:SyncEchar}
summarizes the results of tests that are described in a number of documents
% \cite{syncEtest1}\cite{syncEtest2}\cite{syncEtest3}
available on the WR web-pages
......@@ -330,7 +335,7 @@ The tests results in Table~\ref{tab:SyncEchar} show clearly that the currently a
Although the wander and jitter generation of the WR switch are orders of magnitude better
than required by ITU-T G.8262, the WR switch fails the tests of wander transfer as well as wander
and jitter tolerance. Fig.~\ref{fig:wanderTransfer1} shows that the transfer function of the
WR switch has a bandwidth of 35Hz and a phase gain of 3.3dB at 16Hz while ITU-T G.8262
WR switch has a bandwidth of \textcolor{red}{35Hz} and a phase gain of 3.3dB at 16Hz while ITU-T G.8262
requires a gain smaller than 0.2dB and a bandwidth between 1Hz and 10Hz for EEC-Option~1, and 0.1Hz
for EEC-Option~2.
\begin{figure}[!ht]
......@@ -348,14 +353,14 @@ for EEC-Option~2.
\end{figure}%\vspace{-0.5cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.25\textwidth]{measurements/WRclockChar/wanderTransfer1.jpg}
\includegraphics[width=0.5\textwidth]{measurements/WRclockChar/wanderTransfer1.jpg}
\caption{Transfer function of the WR switch.}
\label{fig:wanderTransfer1}
\end{figure}%\vspace{-0.2cm}
The reasons for the failures of the tests are investigated in section \ref{sec:improvementsSyncE},
which proposes modifications to the SoftPLL that make the WR switch compliant with SyncE. The section
provides measurements of WR performance with the proposed changes.
which proposes modifications to the SoftPLL that make the WR switch compliant with SyncE. Section
\ref{sec:improvementsSyncE} provides also measurements of WR performance with the proposed changes.
The section that follows characterizes L1 syntonisation using phase noise analysis.
......@@ -399,7 +404,7 @@ Fig.~\ref{fig:phaseNoise} shows the results of these three measurements.
% \end{figure}\vspace{-0.3cm}
The effect of gain peaking is clearly visible in the graph. The increase of
phase noise in the 1Hz-10Hz region suggests possible phase noise leaking from the voltage
controlled oscillator (VM53S3). Table~\ref{tab:phaseNoise}
controlled oscillator (VM53S3). Table~\ref{tab:phaseNoise}
% \vspace{-0.2cm}
\begin{table}[!ht]
\centering
......@@ -421,8 +426,11 @@ ext. PLL & 30Hz & SW 1 & 4.4ps & 4.8p
\caption{Integrated RMS jitter in different regions of the spectrum.}
\label{tab:phaseNoise}
\end{table}%\vspace{-0.3cm}
provides the integrated RMS jitter in different regions of the spectrum, i.e. 1Hz to 10Hz,
1Hz to 2kHz and 1Hz to 100kHz. The values of jitter in the first region allow to evaluate
provides the integrated RMS jitter in different regions of the spectrum,
i.e. 1Hz to 10Hz, 1Hz to 2kHz and 1Hz to 100kHz.
\textcolor{red}{The spectrum starts at 1Hz since some of the WR applications \cite{biblio:WR-LIST} require
low jitter at such low frequencies.}
The values of jitter in the first region allow to evaluate
the jitter in the bandwidth of the SoftPLL with respect to the jitter over the entire
measurement bandwidth.
......@@ -473,7 +481,7 @@ are described in the following subsection.
\vspace{-0.1cm}
\subsection{VCO noise leaking}
\label{VCOnoiseLeaking}
The phase noise spectrum of the WR Switch between 1Hz-10Hz suggest \textcolor{red}{an} undesired phase noise
The phase noise spectrum of the WR Switch between 1Hz-10Hz suggest an undesired phase noise
accumulation. We use our simulation model to tune SoftPLL such that the phase noise accumulation
is minimized, which is shown in the measurement results.
......@@ -481,7 +489,7 @@ The measurements discussed in section~\ref{sec:syncEchar} and depicted in
Fig.~\ref{fig:wanderTransfer1} agree closely with the transfer function estimated by our
model of the SoftPLL. We therefore consider the model valid and use it to predict the impact
of leaking of the phase noise from the VCO (VM53S3). The effect of the VCO phase noise, as
estimated from the model, is depicted in Fig.~\ref{fig:slaveVCOLeaking} (red line).
estimated from the model, is depicted in Fig.~\ref{fig:slaveVCOLeaking}-a (red line).
At frequencies between 1Hz and 5Hz, the modelled VCO's leaking phase noise is comparable
with the phase noise of the GM reference (black line). The modelled noise increases to the
phase noise floor in the spectrum of the WR Switch 1 phase noise (blue line).
......@@ -492,7 +500,7 @@ with the VCO rejection characteristics of -58dB@1Hz, -34dB@5Hz and -24db@10Hz (c
with the characteristics of the current SoftPLL: -48dB@1Hz, -20dB@5Hz and -7db@10Hz).
% in Table~\ref{tab:VCOrejectionParams}.
The phase noise
of the WR Switch 1 with modified SoftPLL is depicted in Fig.~\ref{fig:slaveVCOLeaking} (green
of the WR Switch 1 with modified SoftPLL is depicted in Fig.~\ref{fig:slaveVCOLeaking}-a (green
line). The phase noise of WR Switch 1 with modified SoftPLL does not exhibit any
phase noise accumulation in the 1Hz-10Hz range. This improves the Allan Deviation. The new ADEV measurements are
provided in Table~\ref{tab:adev}.
......@@ -513,9 +521,9 @@ provided in Table~\ref{tab:adev}.
\label{fig:slaveVCOLeaking}
\end{figure}%\vspace{-0.3cm}
Theoretically, the larger bandwidth of the modified SoftPLL could lead to
increased jitter due to a less aggressive filtering of the phase noise above 35Hz. However,
increased jitter due to a less aggressive filtering of the phase noise above \textcolor{red}{35Hz}. However,
measurement with a cascade of two WR Switches running the modified SoftPLL and connected to the GM show a decrease
of jitter compared to the non-modified SoftPLL, as presented in
of jitter compared to the non-modified SoftPLL (current), as presented in
Table~\ref{tab:phaseNoise}.
% \vspace{-0.2cm}
\subsection{Syntonisation of GM to the external 10MHz reference}
......@@ -539,7 +547,7 @@ of 1.9kHz) and the digital nature of the DDMTD. The analogue equivalent of
the DDMTD has a low pass filter after the mixer to limit the bandwidth of the measurement
system. The DDMTD has no analogue components. Instead the input phase noise is
filtered by the bandwidth of the D-type flip-flops (hundreds of MHz) and by the filtering action of
the deglitching algorithm \cite{tom}. Consequently, the remaining phase noise is
the deglitching algorithm~\cite{tom}. Consequently, the remaining phase noise is
aliased over the Nyquist bandwidth of the SoftPLL acting as white noise. This effect
can be seen in Fig.~\ref{fig:phaseNoise}.
The Allan Deviation slope of the GM, see Table~\ref{tab:adev}, is the inverse of the
......@@ -552,7 +560,7 @@ of using an external PLL, the available on board AD9516 PLL is used to directly
as the \textit{local PTP clock signal}. This solution allows to verify our suspicions with
minimal changes to the hardware.
Fig.~\ref{fig:improvedGM} provides the results of phase noise measured at the modified GM and
Fig.~\ref{fig:improvedGM}-b provides the results of phase noise measured at the modified GM and
at WR Switch 1 using either the current release of SoftPLL (BW: 30Hz) or its modified version
(BW: 200Hz). The results confirm that the modified GM has a better phase noise profile in the lower
frequencies. This is also confirmed by the values of RMS jitter in Table~\ref{tab:phaseNoise}.
......@@ -596,13 +604,13 @@ SoftPLL.
The SoftPLL fails to pass the wander tolerance tests by unlocking when the modulating
frequency reaches 1Hz and the time amplitude reaches 250ns. Increasing the de-locking
threshold is not a solution since the wander frequency might drive the
local oscillator (VM53S3) out of it's range.
local oscillator (VM53S3) out of its range.
In order to meet the SyncE characteristics without changing the hardware, the SoftPLL
software was modified as follows:
\begin{enumerate}
\item The bandwidth was reduced to 5Hz.
\item Multiple Unit Interval (UI) tracking of error was implemented.
\item Multiple Unit Interval tracking of error was implemented.
\item Locking logic was modified to allow tracking of large zero-mean wander.
\end{enumerate}
......@@ -620,14 +628,14 @@ software was modified as follows:
% based on averaged error, with a 3-second moving window.
% \end{enumerate}
The 3 tests from subsection~\ref{sec:syncEchar} were repeated using the modified
The three tests from subsection~\ref{sec:syncEchar} were repeated using the modified
SoftPLL: wander tolerance (op-1 only), jitter tolerance, and wander transfer. All tests
were successfully passed. The transfer function of the modified SoftPLL is depicted in
Fig.~\ref{fig:SyncEcombo}-1.
% \vspace{-0.3cm}
\vspace{-0.15cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/SyncECompliantCcombo.jpg}
\includegraphics[width=0.48\textwidth]{measurements/WRclockChar/SyncECompliantCcombo.jpg}
\caption{Characteristics of WR switch with SyncE-compliant SoftPLL.}
\label{fig:SyncEcombo}
\end{figure}%\vspace{-0.3cm}
......@@ -635,7 +643,7 @@ It meets the noise transfer (sec. 10 of G.8262)
requirement of below 0.2dB gain peaking and confirms that the bandwidth is within the range
specified for the EEC-option-1. Fig.~\ref{fig:SyncEcombo}-2 shows that the WR switch
with the modified SoftPLL correctly transferred the wander noise defined in
section 9.1.1 of G.8262. The TIE was measured with respect to a CS4000 and shows
section 9.1.1 of G.8262. The TIE was measured with respect to a CS4000 and \textcolor{red}{its plot} shows
the injected wander reference signal (blue) and the signal recovered by the DUT (red).
The DUT tracked the reference signal without losing the lock and quickly followed the reference
signal phase when the wander noise injection finished (at second 17). The switch was able to
......@@ -647,7 +655,7 @@ the WR~PTP is enabled and when it is disabled. In the latter case, the switch is
In order to compare the frequency transfer using the currently available SoftPLL and the
SoftPLL modified to be SyncE compliant, phase noise was measured at WR~Switch~1 using the
setup depicted in Fig.~\ref{fig:phaseNoise} (Microsemi 3120A).
Fig.~\ref{fig:SyncE-compare} shows
Fig.~\ref{fig:SyncE-compare} shows \vspace{-0.2cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.3\textwidth]{measurements/WRclockChar/SyncE-compare.jpg}
......@@ -663,39 +671,39 @@ oscillator with a better phase noise profile in that region (e.g. -70 dBc/Hz at
disparity of performance between the two versions of the SoftPLL.
% \vspace{-0.5cm}
\section{PTP Synchronisation with the modifications}
\section{PTP Synchronisation with modified L1~syntonization}
\label{PTPSynchWithModification}
\textcolor{red}{The performance of the WR PTP synchronisation with the described modifications to the
The performance of the WR PTP synchronisation with the described modifications to the
L1 syntonisation is evaluated in a cascade of 10 WR switches, as depicted in Fig.~\ref{fig:cascade}.
% The switches are connected in a daisy chain using 1m fibers.
The time error between the 10MHz output of the first switch, the Grandmaster, and that of the other
switches is measured over 30min using a 10GS/s oscilloscope. For each version of the Grandmaster, i.e.
the release and the modified version, three measurements are performed,
one for each SoftPLL versions: \\
M1 -- the release version of SoftPLL; \\
M1 -- the SoftPLL in the currently available WR switches; \\
M2 -- the SoftPLL with 200Hz bandwidth described in \ref{VCOnoiseLeaking}; \\
M3 -- the SoftPLL compliant with SyncE described in \ref{sec:improvementsSyncE}.\\
The same version of SoftPLL is used in all the 9 switches.}
The same version of SoftPLL is used in all the 9 switches.
\textcolor{red}{The modifications affect mostly jitter that is calculated as standard deviation of
the measured time error.
The modification of the Grandmaster alone improves jitter as it minimizes
The modifications affect mostly jitter that is calculated as standard deviation of
the measured time error.\begin{figure}[!ht]
\centering
\includegraphics[width=0.49\textwidth]{measurements/WRclockChar/switchCascade.jpg}
\caption{Characteristics of WR switch with SyncE-compliant SoftPLL.}
\label{fig:cascade}
\end{figure}%\vspace{-0.3cm}
The modification of the Grandmaster alone improves jitter as it minimizes
the initial noise that is amplified by the cascaded SoftPLLs. Similarly, increased bandwidth
of the SoftPLL (M2) alone improves jitter as it reduces the amplification of the initial noise.
The best results are achieved when both modifications are applied, in such case the precision
after 9 hops is 11.6ps and the accuracy is below 100ps. }
after 9 hops is 11.6ps and the accuracy is below 100ps.
\textcolor{red}{On the other hand, the SyncE-compliant version
On the other hand, the SyncE-compliant version
of the SoftPLL shows increased jitter and is unable to keep synchronisation after 4 switches.
This is due to the poor phase noise performance below 10Hz of the VM53S3 oscillator, a better
oscillator would help to keep the synchronisation. Still, the measurement shows that the WR PTP synchronisation with the
SyncE-compliant SoftPLL allows sub-ns synchronisation in a chain of 2 switches.}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.45\textwidth]{measurements/WRclockChar/switchCascade.jpg}
\caption{Characteristics of WR switch with SyncE-compliant SoftPLL.}
\label{fig:cascade}
\end{figure}\vspace{-0.3cm}
SyncE-compliant SoftPLL allows sub-ns synchronisation in a chain of 2 switches.
......
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