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papers/ISPCS2016/wrClockCharacteristics.tex
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......@@ -10,8 +10,34 @@
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\title{White Rabbit clock characteristics\vspace{-0.3cm} }
%%%%%%%% title spacing
% \usepackage[compact]{titlesec}
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\title{White Rabbit clock characteristics\vspace{-0.5cm} }
\author{
\IEEEauthorblockN{Mattia Rizzi}
......@@ -103,13 +129,13 @@ This clock has a \textit{time counter} that is a digital time representation
incremented at each rising edge of the \textit{local PTP clock signal}.
The \textit{L1 rx clock signal} is recovered from the reception of data from
the medium while the \textit{L1 tx clock signal} is used in the transmission of data over
the medium.
the medium. %\vspace{-0.2cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{p1588/1588-ha-L1vsPTP.jpg}
\includegraphics[width=0.45\textwidth]{p1588/1588-ha-L1vsPTP.jpg}
\caption{L1 and PTP clock signals.}
\label{fig:clocks}
\end{figure}\vspace{-0.3cm}
\end{figure}%\vspace{-0.3cm}
Unlike in many PTP implementations, in WR the PTP synchronisation and the L1 syntonisation
are made to tightly cooperate. In particular, the local PTP time and the \textit{L1 tx/rx clock signals}
......@@ -143,30 +169,31 @@ rather than manipulating the \textit{time counter} value. The WR PLL not only sy
\textit{L1 rx clock signal} but also maintains the desired phase offset between these two
clock signals, a value so-called \textit{setpoint}. The architecture of the WR PLL is
explained in the next section.
\vspace{-0,4cm}
% \vspace{-0,4cm}
\section{WR Phase-Locked Loop}
The WR PLL, detailed in \cite{tom}, is a phase-shifting digital PLL that uses
Digital Dual Mixer Time Difference (DDMTD) \cite{ddmtd} to obtain the phase error between
the input clock signals.
\vspace{-0,4cm}
% \vspace{-0,4cm}
\subsection{Digital Dual Mixer Time Difference (DDMTD)}
\label{sec:ddmtd}
The DDMTD uses digital mixing to produce output clock signals of lower frequency than that of
the input clock signals. The operation of DDMTD is explained in Fig.~\ref{fig:ddmtd}.
The input clock signals are sampled with D-type flip-flops that are clocked with an offset
clock signal, $clk_{DDMTD}$,
generated from one of the inputs.
generated from one of the inputs.% \vspace{-0.2cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{p1588/1588-ha-dmtd.jpg}
\caption{Digital Dual Mixer Time Difference phase detector.}
\label{fig:ddmtd}
\end{figure}\vspace{-0.2cm}
Its frequency, $f_{DDMTD}$, is very close to that of the input clock signal, $f_{in}$, and
\end{figure}%\vspace{-0.2cm}
Its frequency, $f_{DDMTD}$, is very close to that of the input clock signal, $f_{in}$ and
is specified as follows:
\begin{equation}
\footnotesize
\label{eq:fddmtd}
f_{DDMTD} = \frac{2^N}{1 + 2^N} \cdot f_{in}
\end{equation}
......@@ -179,6 +206,7 @@ the time-difference between the edges of the input and output clock signals is
proportional and can be expressed as follows:
% \vspace{-0,1cm}
\begin{equation}
\footnotesize
\label{eq:fddmtd}
x_{in}[ns] = \frac{1}{1 + 2^N} \cdot x_{out} [ns]
\end{equation}
......@@ -197,13 +225,6 @@ to an input \textit{clock signal} that can be either:
\item the \textit{L1 rx clock signal} recovered at the slave port, or
\item the \textit{clock signal} coming from an external reference.
\end{itemize}
\vspace{-0.4cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{protocol/dmpll_diagram-ML.pdf}
\caption{Overview of the White Rabbit Phase-Locked Loop design.}
\label{fig:WRPLL}
\end{figure}\vspace{-0.2cm}
The outputs of the DDMTD are lower-frequency clock signals, as explained in \ref{sec:ddmtd}.
The rising edges of these signals are
timestamped using a \textit{time counter} incremented by the \textit{DDMTD clock signal}. These timestamps,
......@@ -212,6 +233,13 @@ controller that runs in an embedded CPU \cite{LM32} inside the FPGA. The control
two Voltage-Controlled Crystal Oscillators (VCXO); FRETHE025 generates the \textit{DDMTD clock signal},
VM53S3 generates \textit{local PTP clock signal}. Fig.~\ref{fig:WRPLL} depicts a simplified
block diagram of the WR PLL, which actually consists of two PLLs: Helper and Main.
% \vspace{-0.4cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{protocol/dmpll_diagram-ML.pdf}
\caption{Overview of the White Rabbit Phase-Locked Loop design.}
\label{fig:WRPLL}
\end{figure}%\vspace{-0.2cm}
The \textit{Helper PLL} controls the \textit{DDMTD clock signal}.
This PLL works by comparing the difference between subsequent phase-tags to the
......@@ -234,7 +262,6 @@ its bandwidth is 35Hz.
The SoftPLL determines the characteristics of the frequency transfer through a WR switch. These
are characterised in the next section according to the ITU-T G.8262 guidelines.
\vspace{-0,2cm}
\section{SyncE characteristics of L1 syntonisation}
\label{sec:syncEchar}
......@@ -248,8 +275,8 @@ dedicated to tests \cite{wrTests}.
\scriptsize
\begin{tabular}{|c | c | c | c | c | } \hline
\textbf{Test} & \textbf{G.8262} & \textbf{Test} & \textbf{Measured} & \textbf{Setup} \\
\textbf{name} & \textbf{section}& \textbf{result} & \textbf{values} & \\ \hline
& & & & \\ \hline
\textbf{name} & \textbf{section}& \textbf{result} & \textbf{values} & \\ \hhline{=====}
% & & & & \\ \hline
Frequency offset & 6 & Passed & 4.256ppm & Fig~\ref{fig:allSetups}-1 \\ \hline % ok
Pull-in range & 7.1 & Passed & 8ppm & Fig~\ref{fig:allSetups}-1 \\ \hline % ok
Hold-in range & 7.2 & Passed & & Fig~\ref{fig:allSetups}-1 \\ \hline % ok
......@@ -265,7 +292,7 @@ Wander transfer & 10 & Failed & Fig.~\ref{fig:wanderTrans
\end{tabular}
\caption{WR clock characteristics according to ITU-T G.8262 metrics.}
\label{tab:SyncEchar}
\end{table}\vspace{-0.5cm}
\end{table}%\vspace{-0.2cm}
The table does not include tests of transient response and holdover (section 11 of ITU-T G.8262).
These features are not supported by the current release of the WR switch. Tests of solutions under
development can be found in \cite{syncEtest2}.
......@@ -275,9 +302,8 @@ Calnex Paragon-X, and general-purpose measurement equipment. The measurement set
Fig.~\ref{fig:allSetups} and described below:
\begin{enumerate}
\small
\item A CS4000 Cesium Frequency Standard (Cs) is the external reference for the Paragon-X.
The WR Switch, which is the device under test (DUT), is free-running. The Paragon-X is syntonised
to the DUT over a 1GbE fiber link.
\item A CS4000 Cesium Frequency Standard (Cs) is the external reference for the Paragon-X that
is syntonised to the free-running device under test (DUT) over a 1GbE fiber link.
\item The CS4000 is the external reference for the Paragon-X. The DUT is syntonised to Paragon-X over 1GbE fiber link
connected to port 2 (P2). The Paragon-X is syntonised to the DUT over a 1GbE fiber link on port 1 (P1).
......@@ -296,34 +322,34 @@ Fig.~\ref{fig:allSetups} and described below:
of the GM switch over a 1GbE fiber link. The two CNT-91 TICs are
configured to make Time Interval Error (TIE) measurements of the 10MHz outputs of the
GM and the DUT at a 1kHz sampling rate.
\end{enumerate}\vspace{-0.3cm}
\end{enumerate}%\vspace{-0.3cm}
The tests results in Table~\ref{tab:SyncEchar} show clearly that the currently available WR switches are not compliant with SyncE.
\begin{figure}[!ht]
\centering
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/allSetups.jpg}
\caption{Set-ups used to obtain WR clock characteristics.}
\label{fig:allSetups}
\end{figure}\vspace{-0.3cm}
Although the wander and jitter generation of the WR switch are orders of magnitude better
than required by ITU-T G.8262, the WR switch fails the tests of wander transfer as well as wander
and jitter tolerance. Fig.~\ref{fig:wanderTransfer1} shows that the transfer function of the
WR switch has a bandwidth of 35Hz and a phase gain of 3.3dB at 16Hz while ITU-T G.8262
requires a gain smaller than 0.2dB and a bandwidth between 1Hz and 10Hz for EEC-Option~1, and 0.1Hz
for EEC-Option~2.
\vspace{-0.2cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.45\textwidth]{measurements/WRclockChar/allSetups.jpg}
\caption{Set-ups used to obtain WR clock characteristics.}
\label{fig:allSetups}
\end{figure}%\vspace{-0.3cm}
% \vspace{-0.8cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{measurements/WRclockChar/WanderGen1.jpg}
\caption{Wander generation of the WR switch.}
\label{fig:WanderGen1}
\end{figure}\vspace{-0.5cm}
\end{figure}%\vspace{-0.5cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.25\textwidth]{measurements/WRclockChar/wanderTransfer1.jpg}
\caption{Transfer function of the WR switch.}
\label{fig:wanderTransfer1}
\end{figure}\vspace{-0.2cm}
\end{figure}%\vspace{-0.2cm}
The reasons for the failures of the tests are investigated in section \ref{sec:improvementsSyncE},
which proposes modifications to the SoftPLL that make the WR switch compliant with SyncE. The section
......@@ -335,13 +361,13 @@ The section that follows characterizes L1 syntonisation using phase noise analy
The phase noise of frequency transfer through a WR network is measured to evaluate the
current performance and identify potential improvements. The measurement is done
at each state of a linear daisy chain of 3 WR switches in a setup depicted in Fig.~\ref{fig:phaseNoise-setup}.
\begin{figure}[!ht]\vspace{-0.3cm}
\centering
\includegraphics[width=0.28\textwidth]{measurements/WRclockChar/phaseNoise-setup.jpg}
\caption{Phase noise measurement.}
\label{fig:phaseNoise-setup}
\end{figure}\vspace{-0.3cm}
at each state of a linear daisy chain of 3 WR switches in a setup depicted in Fig.~\ref{fig:phaseNoise}.
% \begin{figure}[!ht]\vspace{-0.3cm}
% \centering
% \includegraphics[width=0.28\textwidth]{measurements/WRclockChar/phaseNoise-setup.jpg}
% \caption{Phase noise measurement.}
% \label{fig:phaseNoise-setup}
% \end{figure}\vspace{-0.3cm}
The measurement setup includes a CS4000 Cesium Frequency Standard,
Microsemi 3120A High-Performance Phase Noise Test Probe, and 3 WR switches.
......@@ -351,22 +377,28 @@ the WR switches. This output provides a 10MHz clock signal derived from the 62.5
\textit{local PTP clock signal} using a AD9516 PLL to minimize additional phase noise.
This setup is used to measure the phase noise of the of \textit{local PTP clock signal}
at the GM WR switch (GM), WR switch 1 (SW1) and WR switch 2 (SW2).
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{measurements/WRclockChar/phaseNoise-setupAndTransfer.jpg}
\caption{Phase noise measurement setup and phase noise transfer.}
\label{fig:phaseNoise}
\end{figure}%\vspace{-0.3cm}
Fig.~\ref{fig:noiseTransfer} shows the results of these three measurements.
Fig.~\ref{fig:phaseNoise} shows the results of these three measurements.
% and indicates the
% estimated phase noise floor. The noise floor is the combined noise estimated by 3120A and the
% probe noise.
\vspace{-0.4cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/noiseTransfer.jpg}
\caption{Phase noise.}
\label{fig:noiseTransfer}
\end{figure}\vspace{-0.3cm}
% \vspace{-0.4cm}
% \begin{figure}[!ht]
% \centering
% \includegraphics[width=0.35\textwidth]{measurements/WRclockChar/noiseTransfer.jpg}
% \caption{Phase noise.}
% \label{fig:noiseTransfer}
% \end{figure}\vspace{-0.3cm}
The effect of gain peaking is clearly visible in the graph. The increase of
phase noise in the 1Hz-10Hz region suggests possible phase noise leaking from the voltage
controlled oscillator (VM53S3). Table~\ref{tab:phaseNoise}
\vspace{-0.2cm}
% \vspace{-0.2cm}
\begin{table}[!ht]
\centering
\scriptsize
......@@ -386,22 +418,14 @@ ext. PLL & 30Hz & SW 1 & 4.4ps & 4.8p
\end{tabular}
\caption{Integrated RMS jitter in different regions of the spectrum.}
\label{tab:phaseNoise}
\end{table}\vspace{-0.3cm}
\end{table}%\vspace{-0.3cm}
provides the integrated RMS jitter in different regions of the spectrum, i.e. 1Hz to 10Hz,
1Hz to 2kHz and 1Hz to 100kHz. The values of jitter in the first region allow to evaluate
the jitter in the bandwidth of the SoftPLL with respect to the jitter over the entire
measurement bandwidth.
Additionally to frequency-domain analysis, Table~\ref{tab:adev} provides time-domain analysis.
Allan Deviation is measured by the Symmetricom 3120A Test Probe at each
of the three switches for different values of integration time with an
equivalent noise bandwidth (ENBW) of 50Hz. Both, Allan Deviation and phase noise analysis
confirm an accumulation of phase noise in the lower frequencies of the spectrum.
The source of the phase noise in the lower frequencies of the spectrum is analysed in the
next section and methods to improve the frequency transfer over WR network are proposed.
\vspace{-0.5cm}
\begin{table}[!ht]
Additionally to frequency-domain analysis, Table~\ref{tab:adev}
\begin{table}[ht]
\centering
\scriptsize
\begin{tabular}{| c |l | c | c | c | c | c | } \hline
......@@ -425,7 +449,16 @@ ext. PLL &SW 2 & 2.9e-10 & 8.3e-11 & 1.3e-11 &
\end{tabular}
\caption{Allan Deviation, equivalent noise bandwidth of 50Hz.}
\label{tab:adev}
\end{table}\vspace{-0.7cm}
\end{table}%\vspace{-0.3cm}
provides time-domain analysis.
Allan Deviation is measured by the Symmetricom 3120A Test Probe at each
of the three switches for different values of integration time with an
equivalent noise bandwidth (ENBW) of 50Hz. Both, Allan Deviation and phase noise analysis
confirm an accumulation of phase noise in the lower frequencies of the spectrum.
The source of the phase noise in the lower frequencies of the spectrum is analysed in the
next section and methods to improve the frequency transfer over WR network are proposed.
% \vspace{-0.5cm}
......@@ -435,7 +468,7 @@ The measurements presented in the previous section indicate that the phase noise
of the frequency transfer in the WR network can be improved at 1) the GM syntonizing
to the external reference, and 2) the WR switches syntonizing to the GM. These improvements
are described in the following subsection.
\vspace{-0.2cm}
\vspace{-0.1cm}
\subsection{VCO noise leaking}
The phase noise spectrum of the WR Switch between 1Hz-10Hz suggest a undesired phase noise
......@@ -461,8 +494,8 @@ of the WR Switch 1 with modified SoftPLL is depicted in Fig.~\ref{fig:slaveVCOLe
line). The phase noise of WR Switch 1 with modified SoftPLL does not exhibit any
phase noise accumulation in the 1Hz-10Hz range. This improves the Allan Deviation. The new ADEV measurements are
provided in Table~\ref{tab:adev}.
\vspace{-0.3cm}
\begin{figure}[!ht]
% \vspace{-0.3cm}
\begin{figure}[ht]
\centering
\includegraphics[width=0.4\textwidth]{measurements/WRclockChar/slaveVCOLeaking.jpg}
\caption{Phase noise.}
......@@ -473,7 +506,7 @@ increased due to a less aggressive filtering of the phase noise above 35Hz. Howe
measurement with a cascade of two WR Switches running the modified SoftPLL and connected to the GM show a decrease
of jitter compared to the non-modified SoftPLL, as presented in
Table~\ref{tab:phaseNoise}.
\vspace{-0.2cm}
% \vspace{-0.2cm}
\subsection{Syntonisation of GM to the external 10MHz reference}
The GM WR Switch locks to the external 10MHz reference using a SoftPLL that requires 62.5MHz
......@@ -496,7 +529,7 @@ system. The DDMTD has no analogue components. Instead the input phase noise is
filtered by the bandwidth of the D-type flip-flops (hundreds of MHz) and by the filtering action of
the deglitching algorithm \cite{tom}. Consequently, the remaining phase noise is
aliased over the Nyquist bandwidth of the SoftPLL acting as white noise. This effect
can be seen in Fig.~\ref{fig:noiseTransfer}.
can be seen in Fig.~\ref{fig:phaseNoise}.
The Allan Deviation slope of the GM, see Table~\ref{tab:adev}, is the inverse of the
integration time which indicates White PM or Flicker PM noise. This is a confirmation of the
aliased white noise in the SoftPLL bandwidth.
......@@ -529,13 +562,13 @@ phase noise accumulation. A controlled oscillator with at least 10dB better phas
1-10Hz spectrum would help to pick
the best noise profile since less bandwidth would be required to reject the noise coming from
the local oscillator.
\vspace{-0.3cm}
% \vspace{-0.3cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/improvedGM.jpg}
\caption{Phase noise.}
\label{fig:improvedGM}
\end{figure}\vspace{-0.3cm}
\end{figure}%\vspace{-0.3cm}
The modification of the GM does not allow the GM to phase-align its \textit{local PTP clock signal}
with the PPS input. Therefore, it has limited usefulness. However, the ongoing design of
......@@ -579,13 +612,13 @@ The 3 tests from subsection~\ref{sec:syncEchar} were repeated using the modified
SoftPLL: wander tolerance (op-1 only), jitter tolerance, and wander transfer. All tests
were successfully passed. The transfer function of the modified SoftPLL is depicted in
Fig.~\ref{fig:SyncEcombo}-1.
\vspace{-0.3cm}
% \vspace{-0.3cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.5\textwidth]{measurements/WRclockChar/SyncECompliantCcombo.jpg}
\caption{Characteristics of WR switch with SyncE-compliant SoftPLL.}
\label{fig:SyncEcombo}
\end{figure}\vspace{-0.3cm}
\end{figure}%\vspace{-0.3cm}
It meets the noise transfer (sec. 10 of G.8262)
requirement of below 0.2dB gain peaking and confirms that the bandwidth is within the range
specified for the EEC-option-1. Fig.~\ref{fig:SyncEcombo}-2 shows that the WR switch
......@@ -601,8 +634,14 @@ the WR PTP is enabled and when it is disabled. In the latter case, the switch is
In order to compare the frequency transfer using the currently available SoftPLL and the
SoftPLL modified to be SyncE compliant, phase noise was measured at WR~Switch~1 using the
setup depicted in Fig.~\ref{fig:phaseNoise-setup} (Microsemi 3120A).
setup depicted in Fig.~\ref{fig:phaseNoise} (Microsemi 3120A).
Fig.~\ref{fig:SyncE-compare} shows
\begin{figure}[!ht]
\centering
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/SyncE-compare.jpg}
\caption{Phase noise transfer.}
\label{fig:SyncE-compare}
\end{figure}%\vspace{-0.5cm}
that the unmodified SoftPLL (blue) has a very low integrated jitter of 4ps RMS (from 1Hz to 100kHz).
The SyncE-compliant SoftPLL (pink) has a much higher jitter in the 1-10Hz bandwidth that results
in a total integrated jitter of 100ps RMS. This is attributed to the the VCO (VM53S3)
......@@ -610,13 +649,8 @@ that exhibits high phase noise in the 1-10Hz region when not controlled (red tra
An
oscillator with a better phase noise profile in that region (e.g. -70 dBc/Hz at 1Hz) can lower the
disparity of performance between the two versions of the SoftPLL.
\vspace{-0.5cm}
\begin{figure}[!ht]
\centering
\includegraphics[width=0.35\textwidth]{measurements/WRclockChar/SyncE-compare.jpg}
\caption{Phase noise transfer.}
\label{fig:SyncE-compare}
\end{figure}\vspace{-0.5cm}
% \vspace{-0.5cm}
\section{Conclusions}
\label{conclusions}
......
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