Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
White Rabbit
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
5
Issues
5
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
White Rabbit
Commits
ef1c83d3
Commit
ef1c83d3
authored
Jun 08, 2018
by
Javier Serrano
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Some modifications after discussing with Dimitris and Enrico
parent
762dca72
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
54 additions
and
74 deletions
+54
-74
wr_efts_2018.tex
presentations/WR_Javier_EFTS_2018/wr_efts_2018.tex
+54
-74
No files found.
presentations/WR_Javier_EFTS_2018/wr_efts_2018.tex
View file @
ef1c83d3
...
@@ -139,8 +139,8 @@
...
@@ -139,8 +139,8 @@
\item
Ethernet features (VLAN)
\&
protocols (SNMP)
\item
Ethernet features (VLAN)
\&
protocols (SNMP)
\end{itemize}
\end{itemize}
\begin{itemize}
\begin{itemize}
\item
\color
{
Blue
}{
High accuracy synchroniz
ation
}
\item
\color
{
Blue
}{
Sub-ns synchronis
ation
}
\item
\color
{
Red
}{
Reliable and low-latency Control Data
}
\item
\color
{
Red
}{
Guaranteed (by design) upper bound in frame latency
}
\end{itemize}
\end{itemize}
\column
{
.6
\textwidth
}
\column
{
.6
\textwidth
}
...
@@ -190,67 +190,31 @@
...
@@ -190,67 +190,31 @@
\begin{frame}
{
White Rabbit technology
}
\begin{frame}
{
White Rabbit technology
}
\begin{block}
{
Based on
}
\begin{block}
{
Based on
}
\begin{itemize}
\begin{itemize}
\item
Gigabit Ethernet over fib
er
\item
Gigabit Ethernet over fib
re
\item
IEEE-1588 protocol
\item
IEEE-1588 protocol
\end{itemize}
\end{itemize}
\end{block}
\end{block}
\pause
\pause
\begin{block}
{
Enhanced with
}
\begin{block}
{
Enhanced with
}
\begin{itemize}
\begin{itemize}
\item
Layer 1 syntoni
z
ation
\item
Layer 1 syntoni
s
ation
\item
Digital Dual Mixer Time Difference (DDMTD)
\item
Digital Dual Mixer Time Difference (DDMTD)
\item
Link delay model
\item
Link delay model
\end{itemize}
\end{itemize}
\end{block}
\end{block}
\end{frame}
\end{frame}
\begin{frame}
{
Open Systems Interconnection(OSI) network model
}
\begin{center}
\includegraphics
<1>[width=.6
\textwidth
]
{
misc/osi
_
layers
_
0.pdf
}
\includegraphics
<2>[width=.6
\textwidth
]
{
misc/osi
_
layers
_
7.pdf
}
\includegraphics
<3>[width=.6
\textwidth
]
{
misc/osi
_
layers
_
6.pdf
}
\includegraphics
<4>[width=.6
\textwidth
]
{
misc/osi
_
layers
_
5.pdf
}
\includegraphics
<5>[width=.6
\textwidth
]
{
misc/osi
_
layers
_
4.pdf
}
\includegraphics
<6>[width=.6
\textwidth
]
{
misc/osi
_
layers
_
3.pdf
}
\includegraphics
<7>[width=.6
\textwidth
]
{
misc/osi
_
layers
_
2.pdf
}
\includegraphics
<8>[width=.6
\textwidth
]
{
misc/osi
_
layers
_
1.pdf
}
\end{center}
\end{frame}
\begin{frame}
{
Ethernet switches in a nutshell
}
\begin{center}
\includegraphics
<1>[width=.6
\textwidth
]
{
misc/osi
_
layers
_
eth
_
sw.pdf
}
\includegraphics
<2->[width=.3
\textheight
]
{
misc/home
_
switch.png
}
\includegraphics
<2->[width=.7
\textheight
]
{
misc/prof
_
switch.png
}
\includegraphics
<2>[width=.8
\textwidth
]
{
misc/switch
_
in
_
nutshell
_
mac.pdf
}
\includegraphics
<3>[width=.8
\textwidth
]
{
misc/switch
_
in
_
nutshell
_
1-2
_
mac.pdf
}
\includegraphics
<4>[width=.8
\textwidth
]
{
misc/switch
_
in
_
nutshell
_
1-3
_
mac.pdf
}
\includegraphics
<5>[width=.8
\textwidth
]
{
misc/switch
_
in
_
nutshell
_
1-2
_
3-1
_
mac.pdf
}
\end{center}
\end{frame}
\begin{frame}
{
White Rabbit in OSI model
}
\begin{center}
\includegraphics
<1>[width=.6
\textwidth
]
{
misc/osi
_
layers
_
WR.pdf
}
\end{center}
%\begin{center}
% \begin{adjustwidth}{-1.5em}{-1.5em}
% \includegraphics<2>[width=1.1\textwidth]{misc/switch-and-osi.pdf}
% \end{adjustwidth}
%\end{center}
\end{frame}
\begin{frame}
{
White Rabbit technology
}
\begin{frame}
{
White Rabbit technology
}
\begin{block}
{
Based on
}
\begin{block}
{
Based on
}
\begin{itemize}
\begin{itemize}
\item
Gigabit Ethernet over fib
er
\item
Gigabit Ethernet over fib
re
\item
IEEE-1588 protocol
\item
IEEE-1588 protocol
\end{itemize}
\end{itemize}
\end{block}
\end{block}
\begin{block}
{
Enhanced with
}
\begin{block}
{
Enhanced with
}
\begin{itemize}
\begin{itemize}
\item
Layer 1 syntoni
z
ation
\item
Layer 1 syntoni
s
ation
\item
Digital Dual Mixer Time Difference (DDMTD)
\item
Digital Dual Mixer Time Difference (DDMTD)
\item
Link delay model
\item
Link delay model
\end{itemize}
\end{itemize}
...
@@ -265,7 +229,7 @@
...
@@ -265,7 +229,7 @@
\end{center}
\end{center}
\column
{
.75
\textwidth
}
\column
{
.75
\textwidth
}
\begin{itemize}
\begin{itemize}
\item
Frame-based synchroni
z
ation protocol.
\item
Frame-based synchroni
s
ation protocol.
\item
Simple calculations:
\item
Simple calculations:
\begin{itemize}
\begin{itemize}
\item
link
$
delay
_{
ms
}$
$
\delta
_{
ms
}
=
\frac
{
(
t
_{
4
}
-
t
_{
1
}
)
-
(
t
_{
3
}
-
t
_{
2
}
)
}{
2
}$
\item
link
$
delay
_{
ms
}$
$
\delta
_{
ms
}
=
\frac
{
(
t
_{
4
}
-
t
_{
1
}
)
-
(
t
_{
3
}
-
t
_{
2
}
)
}{
2
}$
...
@@ -281,7 +245,7 @@
...
@@ -281,7 +245,7 @@
\end{columns}
\end{columns}
\end{frame}
\end{frame}
\begin{frame}
{
Layer 1 Syntoni
z
ation
}
\begin{frame}
{
Layer 1 Syntoni
s
ation
}
%\begin{block}{Common clock for the entire network}
%\begin{block}{Common clock for the entire network}
\begin{itemize}
\begin{itemize}
\item
All network devices use the same physical layer clock.
\item
All network devices use the same physical layer clock.
...
@@ -309,15 +273,6 @@
...
@@ -309,15 +273,6 @@
\end{frame}
\end{frame}
%\begin{frame}{Deglitching algorithm -- to backup slides?}
%\end{frame}
\begin{frame}
{
SoftPLL
}
\begin{center}
\includegraphics
[width=.9\textwidth]
{
protocol/dmpll
_
diagram-slides.pdf
}
\end{center}
\end{frame}
\begin{frame}
{
Link delay model
}
\begin{frame}
{
Link delay model
}
\begin{center}
\begin{center}
\includegraphics
[width=0.9\textwidth]
{
calibration/link-model.pdf
}
\includegraphics
[width=0.9\textwidth]
{
calibration/link-model.pdf
}
...
@@ -325,7 +280,7 @@
...
@@ -325,7 +280,7 @@
\begin{itemize}
\begin{itemize}
\item
static hardware delays:
$
\Delta
_{
TXM
}$
,
$
\Delta
_{
RXM
}$
,
$
\Delta
_{
TXS
}$
,
$
\Delta
_{
RXS
}$
\item
static hardware delays:
$
\Delta
_{
TXM
}$
,
$
\Delta
_{
RXM
}$
,
$
\Delta
_{
TXS
}$
,
$
\Delta
_{
RXS
}$
\item
semi-static hardware delays:
$
\epsilon
_
M
$
,
$
\epsilon
_
S
$
\item
semi-static hardware delays:
$
\epsilon
_
M
$
,
$
\epsilon
_
S
$
\item
fib
er
asymmetry coefficient:
$
\alpha
=
\frac
{
\delta
_{
MS
}
-
\delta
_{
SM
}}{
\delta
_{
SM
}}$
\item
fib
re
asymmetry coefficient:
$
\alpha
=
\frac
{
\delta
_{
MS
}
-
\delta
_{
SM
}}{
\delta
_{
SM
}}$
\end{itemize}
\end{itemize}
\pause
\pause
\begin{block}
{}
\begin{block}
{}
...
@@ -420,25 +375,61 @@
...
@@ -420,25 +375,61 @@
\end{frame}
\end{frame}
\frame
{
\frametitle
{
An aside: PLL block diagram
}
\includegraphics
[width=\textwidth]
{
misc/pll
_
model.pdf
}
}
\frame
{
\frametitle
{
An aside: PLL transfer functions
}
\begin{block}
{
Total output phase spectrum
}
$
\Phi
_
o
(
s
)
=
H
(
s
)
\cdot
\Phi
_
i
(
s
)
+
E
(
s
)
\cdot
\Phi
_
n
(
s
)
$
\end{block}
\begin{block}
{
System transfer function (low pass)
}
$
H
(
s
)
=
\frac
{
K
_{
VCO
}
K
_
d F
(
s
)
}{
s
+
K
_{
VCO
}
K
_
d F
(
s
)
}
$
\end{block}
\begin{block}
{
Error transfer function (high pass)
}
$
E
(
s
)
=
1
-
H
(
s
)
=
\frac
{
s
}{
s
+
K
_{
VCO
}
K
_
d F
(
s
)
}
$
\end{block}
}
\frame
{
\frametitle
{
An aside: jitter optimisation
}
\includegraphics
[height=0.7\textwidth]
{
misc/pll
_
psd.pdf
}
}
\begin{frame}
{
Test setup for 10MHz switch output
}
\begin{center}
\includegraphics
[width=\textwidth]
{
measurements/WRSlowJitter/rsz
_
experimental
_
setup.png
}
\end{center}
\end{frame}
\begin{frame}
{
WR switch clocking scheme
}{
Thanks to Mattia Rizzi for the work and
the figures in this section
}
\begin{center}
\includegraphics
[width=.85\textwidth]
{
switch/wrs
_
v3
_
3
_
clocking.png
}
\end{center}
\end{frame}
\begin{frame}
{
MMCM noise
}
\begin{center}
\includegraphics
[height=.7\textheight]
{
switch/mmcm
_
noise.png
}
\end{center}
\end{frame}
\begin{frame}
{
WR Switch: low jitter daughterboard
}
\begin{frame}
{
WR Switch: low jitter daughterboard
}
\begin{columns}
\begin{columns}
\column
{
.35
\textwidth
}
\column
{
.35
\textwidth
}
\includegraphics
[width=.8\textheight, angle=90]
{
measurements/WRSlowJitter/rsz
_
3d
_
image
__
1
_
.jpg
}
\includegraphics
[width=.8\textheight, angle=90]
{
measurements/WRSlowJitter/rsz
_
3d
_
image
__
1
_
.jpg
}
\column
{
.65
\textwidth
}
\column
{
.65
\textwidth
}
\begin{itemize}
\begin{itemize}
\item
Current release of WRS in GM mode has suboptimal performance on both jitter (9ps RMS 1Hz-100kHz) and ADEV (1.4E-11
$
\tau
$
=1s ENBW 50Hz)
\item
Current release of WRS in GM mode has sub
-
optimal performance on both jitter (9ps RMS 1Hz-100kHz) and ADEV (1.4E-11
$
\tau
$
=1s ENBW 50Hz)
\item
A daughterboard was designed, produced and tested to improve the performance
\item
A daughterboard was designed, produced and tested to improve the performance
\item
Modified WRS improves performance on both jitter (
$
<
$
2ps RMS 10Hz-100kHz) and ADEV (
$
<
$
5E-13
$
\tau
$
=1s ENBW 50Hz) in GM mode
\item
Modified WRS improves performance on both jitter (
$
<
$
2ps RMS 10Hz-100kHz) and ADEV (
$
<
$
5E-13
$
\tau
$
=1s ENBW 50Hz) in GM mode
\end{itemize}
\end{itemize}
\end{columns}
\end{columns}
\end{frame}
\end{frame}
\begin{frame}
{
Daughterboard Test Setup
}
\begin{center}
\includegraphics
[width=\textwidth]
{
measurements/WRSlowJitter/rsz
_
experimental
_
setup.png
}
\end{center}
\end{frame}
\begin{frame}
{
Test Results in GM mode: PM noise
}
\begin{frame}
{
Test Results in GM mode: PM noise
}
\begin{center}
\begin{center}
\includegraphics
[height=.85\textheight]
{
measurements/WRSlowJitter/pn.png
}
\includegraphics
[height=.85\textheight]
{
measurements/WRSlowJitter/pn.png
}
...
@@ -451,17 +442,6 @@
...
@@ -451,17 +442,6 @@
\end{center}
\end{center}
\end{frame}
\end{frame}
\begin{frame}
{
Test Results in Slave mode: PM noise
}
\begin{center}
\includegraphics
[height=.85\textheight]
{
measurements/WRSlowJitter/slave
_
pn.png
}
\end{center}
\end{frame}
\begin{frame}
{
Test Results in Slave mode: Modified ADEV
}
\begin{center}
\includegraphics
[height=.85\textheight]
{
measurements/WRSlowJitter/slave
_
mdev.png
}
\end{center}
\end{frame}
\section
{
Current developments
}
\section
{
Current developments
}
\subsection
{}
\subsection
{}
...
@@ -472,14 +452,14 @@
...
@@ -472,14 +452,14 @@
networks as well as improving the phase noise and performing extensive network stress tests.
networks as well as improving the phase noise and performing extensive network stress tests.
\end{block}
\end{block}
\pause
\pause
\begin{block}
{
Standardi
z
ation
}
\begin{block}
{
Standardi
s
ation
}
IEEE 1588 revision process is ongoing and contains a sub-committee (High
IEEE 1588 revision process is ongoing and contains a sub-committee (High
Accuracy) dedicated to White Rabbit. Revised standard expected in 2019.
Accuracy) dedicated to White Rabbit. Revised standard expected in 2019.
\end{block}
\end{block}
\pause
\pause
\begin{block}
{
Robustness
}
\begin{block}
{
Robustness
}
Based on redundant information and fast switch-over between
Based on redundant information and fast switch-over between
redundant fib
er
s and switches.
redundant fib
re
s and switches.
\end{block}
\end{block}
\end{frame}
\end{frame}
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment