V3 SCH/PCB: connect 10 MHz external reference to a GCLK FPGA pin
Add a 0-ohm resistor (mounted by default) connecting the REF_10M net to any 3.3V GCLK pin of the FPGA. This is required for efficient operation of BB phase detector locking the 125 MHz ethernet clock to external 10 MHz reference. The C185 connecting REF_10M to AD9516 should not be mounted by default.