Makefile 469 Bytes
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SOURCES = cgen_c_headers.lua  cgen_common.lua  cgen_verilog.lua  cgen_vhdl.lua  target_wishbone.lua  wbgen_common.lua  wbgen_main.lua  wbgen_rams.lua  wbgen_regbank.lua  wbgen_eic.lua
OUTPUT = wbgen2

VHDL_LIBRARY = lib/wbgen2_dpssram.vhd lib/wbgen2_eic.vhd
VERILOG_LIBRARY = $(VHDL_LIBRARY:.vhd=.v)

all:	$(SOURCES) 
#		make -C utils/vhd2vl/src
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		./squish
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		chmod +x wbgen2

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.PHONY: all clean

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%.v:	%.vhd
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		./utils/vhd2vl/src/vhd2vl $^ > $@

clean:
		rm -rf $(OUTPUT)