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Wishbone slave generator
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Wishbone slave generator
Commits
2113b3eb
Commit
2113b3eb
authored
Dec 05, 2012
by
Tomasz Wlostowski
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added reset value option (single-bit registers only, wip)
parent
4bc4cbc9
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1 changed file
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2 additions
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1 deletion
+2
-1
wbgen_regbank.lua
wbgen_regbank.lua
+2
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wbgen_regbank.lua
View file @
2113b3eb
...
...
@@ -129,7 +129,8 @@ function gen_hdl_code_bit(field, reg)
field
.
write_code
=
{
--va(vi("rddata_reg", field.offset), vundefined()),
va
(
prefix
..
"_int"
,
vi
(
"wrdata_reg"
,
field
.
offset
))
};
field
.
read_code
=
{
va
(
vi
(
"rddata_reg"
,
field
.
offset
),
prefix
..
"_int"
)
};
field
.
reset_code_main
=
{
va
(
prefix
..
"_int"
,
0
)
};
print
(
"RV: "
,
field
.
reset_value
)
field
.
reset_code_main
=
{
va
(
prefix
..
"_int"
,
csel
(
field
.
reset_value
==
nil
,
0
,
field
.
reset_value
))
};
field
.
extra_code
=
{
va
(
prefix
..
"_o"
,
prefix
..
"_int"
)
};
elseif
(
field
.
access
==
ACC_RO_WO
)
then
...
...
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