Commit 397f0878 authored by twlostow's avatar twlostow

bugfix: unused bits loaded with 'X's on read

git-svn-id: http://svn.ohwr.org/wishbone-gen@2 4537843c-45c2-4d80-8546-c3283569414f
parent 7c043042
......@@ -80,7 +80,7 @@ function cgen_vhdl_entity()
if(i == table.getn(g_portlist)) then last = true; else last = false; end
-- if we have a comment associated with current port, let's emit it before the port definition.
if(port.comment ~= nil) then
if(port.comment ~= nil and port.comment ~= "") then
emitx("-- "..port.comment.."\n");
end
......
......@@ -105,10 +105,9 @@ function gen_bus_logic_wishbone()
local rwcode = {
vif(vequal("wb_we_i" ,1), {
wcode,
padcode
}, {
rcode
rcode,
padcode
}); };
table_join(rwcode, { va(vi("ack_sreg", math.max(acklen-1, 0)), 1); } );
......
......@@ -928,7 +928,7 @@ function cgen_vhdl_entity()
if(i == table.getn(g_portlist)) then last = true; else last = false; end
-- if we have a comment associated with current port, let's emit it before the port definition.
if(port.comment ~= nil) then
if(port.comment ~= nil and port.comment ~= "") then
emitx("-- "..port.comment.."\n");
end
......@@ -4002,10 +4002,9 @@ function gen_bus_logic_wishbone()
local rwcode = {
vif(vequal("wb_we_i" ,1), {
wcode,
padcode
}, {
rcode
rcode,
padcode
}); };
table_join(rwcode, { va(vi("ack_sreg", math.max(acklen-1, 0)), 1); } );
......
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