Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
Wishbone slave generator
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
24
Issues
24
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Wishbone slave generator
Commits
4bc4cbc9
Commit
4bc4cbc9
authored
Oct 25, 2012
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
added texinfo documentation target (unfinished)
parent
a0b44645
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
165 additions
and
6 deletions
+165
-6
cgen_doc_texinfo.lua
cgen_doc_texinfo.lua
+146
-0
squishy
squishy
+1
-0
wbgen_main.lua
wbgen_main.lua
+18
-6
No files found.
cgen_doc_texinfo.lua
0 → 100644
View file @
4bc4cbc9
#!/usr/bin/lua
-- wbgen2, (c) 2010 Tomasz Wlostowski/CERN BE-Co-HT
-- LICENSED UNDER GPL v2
-- File: cgen_c_headers.lua
--
-- Texinfo documentation generator.
--
--function has_any_ports(reg)
-- local has = false;
-- if(reg.ports ~= nil) then return true; end
-- foreach_subfield(reg, function(field) if (field.ports ~= nil) then has = true; end end);
-- return has;
--end
function
format_tex_string
(
s
)
s
=
string.gsub
(
s
,
" +"
,
" "
);
s
=
string.gsub
(
s
,
"^%-"
,
"@bullet{} "
);
s
=
string.gsub
(
s
,
"
\n
%-"
,
"@*@bullet{} "
);
s
=
string.gsub
(
s
,
"
\n
"
,
"@*"
);
s
=
string.gsub
(
s
,
"<b>"
,
"@b{"
);
s
=
string.gsub
(
s
,
"</b>"
,
"}"
);
s
=
string.gsub
(
s
,
"<i>"
,
"@b{"
);
s
=
string.gsub
(
s
,
"</i>"
,
"}"
);
s
=
string.gsub
(
s
,
"<code>"
,
"@code{"
);
s
=
string.gsub
(
s
,
"</code>"
,
"}"
);
return
s
end
function
cgen_tex_memmap
()
local
evenodd
=
0
;
local
n
=
2
;
emit
(
"@subsubsection Memory map summary"
);
emit
(
"@multitable @columnfractions .10 .15 .15 .55"
)
emit
(
"@headitem Address @tab Type @tab Prefix @tab Name"
)
foreach_reg
({
TYPE_REG
},
function
(
reg
)
if
(
reg
.
full_hdl_prefix
~=
nil
)
then
emit
(
string.format
(
"@item @code{0x%x} @tab"
,
reg
.
base
*
4
));
if
(
reg
.
doc_is_fiforeg
==
nil
)
then
emit
(
"REG @tab"
);
else
emit
(
"FIFOREG @tab"
);
end
emit
(
"@code{"
..
reg
.
c_prefix
..
"} @tab"
);
emit
(
reg
.
name
);
end
end
);
foreach_reg
({
TYPE_RAM
},
function
(
reg
)
if
(
reg
.
full_hdl_prefix
~=
nil
)
then
emit
(
string.format
(
"@item @code{0x%x - 0x%x}"
,
reg
.
base
,
reg
.
base
+
math.pow
(
2
,
reg
.
wrap_bits
)
*
reg
.
size
-
1
));
emit
(
"@tab MEM @tab @code{"
..
reg
.
c_prefix
..
"} @tab "
..
reg
.
name
);
end
end
);
emit
(
"@end multitable "
)
end
function
cgen_tex_access
(
acc
)
if
(
acc
==
READ_ONLY
)
then
return
"R/O"
;
elseif
(
acc
==
READ_WRITE
)
then
return
"R/W"
;
elseif
(
acc
==
WRITE_ONLY
)
then
return
"W/O"
;
else
return
"FIXME!"
;
end
end
function
cgen_texinfo_reg
(
reg
)
emit
(
"@subsubsection @code{"
..
reg
.
c_prefix
..
"} - "
..
reg
.
name
);
cur_reg_no
=
cur_reg_no
+
1
;
local
tbl
=
htable_new
(
4
,
2
);
-- fixme: FIFO regs
-- emit("Address: @code{"..string.format("0x%x", reg.base * (DATA_BUS_WIDTH/8)).."}");
if
(
reg
.
description
~=
nil
)
then
emit
(
reg
.
description
);
end
emit
(
"@multitable @columnfractions .10 .10 .15 .10 .55"
)
emit
(
"@headitem Bits @tab Access @tab Prefix @tab Default @tab Name"
)
foreach_subfield
(
reg
,
function
(
field
)
-- emit("@columnfractions .10 .10 .15 .10 .55")
if
(
field
.
size
==
1
)
then
emit
(
string.format
(
"@item @code{%d}"
,
field
.
offset
));
else
emit
(
string.format
(
"@item @code{%d...%d}"
,
field
.
offset
+
field
.
size
-
1
,
field
.
offset
));
end
emit
(
"@tab "
..
cgen_tex_access
(
field
.
access_bus
)
..
" @tab"
);
if
(
field
.
c_prefix
==
nil
)
then
-- anonymous field?
emit
(
"@code{"
..
string.upper
(
reg
.
c_prefix
)
..
"}"
);
else
emit
(
"@code{"
..
string.upper
(
field
.
c_prefix
)
..
"}"
);
end
emit
(
"@tab @code{X} @tab "
);
emit
(
field
.
name
);
-- emit("@columnfractions 1")
-- emit("@item dupa")
--if(field.description ~= nil) then
-- emit("<br>"..string.gsub(field.description, "\n", "<br>"));
--end
end
);
emit
(
"@end multitable"
);
emit
(
"@multitable @columnfractions 0.15 0.85"
)
emit
(
"@headitem Field @tab Description"
)
foreach_subfield
(
reg
,
function
(
field
)
if
(
field
.
description
~=
nil
)
then
pfx
=
csel
(
field
.
c_prefix
==
nil
,
reg
.
c_prefix
,
field
.
c_prefix
)
emit
(
"@item @code{"
..
pfx
..
"} @tab "
..
format_tex_string
(
field
.
description
));
end
end
);
emit
(
"@end multitable"
);
end
function
cgen_generate_texinfo_documentation
()
cgen_new_snippet
();
cgen_tex_memmap
();
foreach_reg
({
TYPE_REG
},
function
(
reg
)
if
(
reg
.
no_docu
==
nil
or
reg
.
no_docu
==
false
)
then
cgen_texinfo_reg
(
reg
);
end
end
);
cgen_write_current_snippet
();
end
\ No newline at end of file
squishy
View file @
4bc4cbc9
...
@@ -13,6 +13,7 @@ Main "cgen_vhdl.lua"
...
@@ -13,6 +13,7 @@ Main "cgen_vhdl.lua"
Main "cgen_verilog.lua"
Main "cgen_verilog.lua"
Main "cgen_c_headers.lua"
Main "cgen_c_headers.lua"
Main "cgen_doc.lua"
Main "cgen_doc.lua"
Main "cgen_doc_texinfo.lua"
Main "wbgen_regbank.lua"
Main "wbgen_regbank.lua"
Main "wbgen_rams.lua"
Main "wbgen_rams.lua"
Main "wbgen_eic.lua"
Main "wbgen_eic.lua"
...
...
wbgen_main.lua
View file @
4bc4cbc9
...
@@ -27,6 +27,7 @@ options.register_data_output = false;
...
@@ -27,6 +27,7 @@ options.register_data_output = false;
options
.
lang
=
"vhdl"
;
options
.
lang
=
"vhdl"
;
options
.
c_reg_style
=
"struct"
;
options
.
c_reg_style
=
"struct"
;
options
.
hdl_reg_style
=
"signals"
;
options
.
hdl_reg_style
=
"signals"
;
options
.
doc_format
=
"html"
require
"alt_getopt"
require
"alt_getopt"
...
@@ -35,7 +36,8 @@ local usage_string = [[slave Wishbone generator
...
@@ -35,7 +36,8 @@ local usage_string = [[slave Wishbone generator
local
commands_string
=
[[options:
local
commands_string
=
[[options:
-C, --co=FILE Write the slave's generated C header file to FILE
-C, --co=FILE Write the slave's generated C header file to FILE
-D, --doco=FILE Write the slave's generated HTML documentation to FILE
-f, --docformat=FORMAT Write documentation for texinfo or HTML (defaults to HTML)
-D, --doco=FILE Write the slave's generated documentation to FILE
-h, --help Show this help text
-h, --help Show this help text
-l, --lang=LANG Set the output Hardware Description Language (HDL) to LANG
-l, --lang=LANG Set the output Hardware Description Language (HDL) to LANG
Valid values for LANG: {vhdl,verilog}
Valid values for LANG: {vhdl,verilog}
...
@@ -49,7 +51,7 @@ local commands_string = [[options:
...
@@ -49,7 +51,7 @@ local commands_string = [[options:
-p, --vpo=FILE Generate a VHDL package for slave's generated VHDL
-p, --vpo=FILE Generate a VHDL package for slave's generated VHDL
(necessary with --hstyle=record)
(necessary with --hstyle=record)
wbgen2 (c) Tomasz Wlostowski/CERN BE-CO-HT 2010]]
wbgen2 (c) Tomasz Wlostowski/CERN BE-CO-HT 2010
-2012
]]
function
usage
()
function
usage
()
print
(
usage_string
)
print
(
usage_string
)
...
@@ -66,19 +68,20 @@ function parse_args(arg)
...
@@ -66,19 +68,20 @@ function parse_args(arg)
help
=
"h"
,
help
=
"h"
,
version
=
"v"
,
version
=
"v"
,
co
=
"C"
,
co
=
"C"
,
docformat
=
"f"
,
doco
=
"D"
,
doco
=
"D"
,
constco
=
"K"
,
constco
=
"K"
,
lang
=
"l"
,
lang
=
"l"
,
vo
=
"V"
,
vo
=
"V"
,
vpo
=
"p"
,
vpo
=
"p"
,
cstyle
=
"s"
,
cstyle
=
"s"
,
hstyle
=
"H"
hstyle
=
"H"
}
}
local
optarg
local
optarg
local
optind
local
optind
optarg
,
optind
=
alt_getopt
.
get_opts
(
arg
,
"hvC:D:K:l:V:s:H:p:"
,
long_opts
)
optarg
,
optind
=
alt_getopt
.
get_opts
(
arg
,
"hvC:D:K:l:V:s:
f:
H:p:"
,
long_opts
)
for
key
,
value
in
pairs
(
optarg
)
do
for
key
,
value
in
pairs
(
optarg
)
do
if
key
==
"h"
then
if
key
==
"h"
then
usage_complete
()
usage_complete
()
...
@@ -97,6 +100,9 @@ function parse_args(arg)
...
@@ -97,6 +100,9 @@ function parse_args(arg)
elseif
key
==
"K"
then
elseif
key
==
"K"
then
options
.
output_vlog_constants_file
=
value
options
.
output_vlog_constants_file
=
value
elseif
key
==
"f"
then
options
.
doc_format
=
value
elseif
key
==
"l"
then
elseif
key
==
"l"
then
options
.
lang
=
value
options
.
lang
=
value
if
(
options
.
lang
~=
"vhdl"
and
options
.
lang
~=
"verilog"
)
then
if
(
options
.
lang
~=
"vhdl"
and
options
.
lang
~=
"verilog"
)
then
...
@@ -201,7 +207,13 @@ end
...
@@ -201,7 +207,13 @@ end
if
(
options
.
output_doc_file
~=
nil
)
then
if
(
options
.
output_doc_file
~=
nil
)
then
cgen_generate_init
(
options
.
output_doc_file
);
cgen_generate_init
(
options
.
output_doc_file
);
cgen_generate_documentation
();
if
(
options
.
doc_format
==
"html"
)
then
cgen_generate_html_documentation
();
else
cgen_generate_texinfo_documentation
();
end
cgen_generate_done
();
cgen_generate_done
();
end
end
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment