Commit 54091524 authored by twlostow's avatar twlostow

bugfix: VHDL code error in case() statement generation for <3 cases

git-svn-id: http://svn.ohwr.org/wishbone-gen@18 4537843c-45c2-4d80-8546-c3283569414f
parent dcd6b1f9
......@@ -19,6 +19,10 @@ fieldtype_2_vhdl[SLV] = "std_logic_vector";
-- generates a string containing VHDL-compatible numeric constant of value [value] and size [numbits]
function gen_vhdl_bin_literal(value, numbits)
if(numbits == 1) then
return string.format("'%d'", csel(value==0,0,1));
end
local str ='\"';
local i,n,d,r;
......@@ -352,7 +356,8 @@ function cgen_generate_vhdl_code(tree)
if(tsd.type == BIT) then
return("'"..tss.name.."'");
elseif(tsd.type == SLV) then
return("std_logic_vector(to_unsigned("..tss.name..", "..calc_size(tsd).."))");
-- return("std_logic_vector(to_unsigned("..tss.name..", "..calc_size(tsd).."))");
return gen_vhdl_bin_literal(tss.name, calc_size(tsd));
elseif(tsd.type == SIGNED) then
return("to_signed("..tss.name..", "..calc_size(tsd)..")");
elseif(tsd.type == UNSIGNED) then
......
......@@ -55,9 +55,9 @@ architecture rtl of wbgen2_fifo_sync is
rdreq : in std_logic;
empty : out std_logic;
clock : in std_logic;
q : out std_logic_vector (12 downto 0);
q : out std_logic_vector (g_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector (12 downto 0);
data : in std_logic_vector (g_width-1 downto 0);
full : out std_logic
);
end component;
......
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