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Wishbone slave generator
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Wishbone slave generator
Commits
6b6a3b7e
Commit
6b6a3b7e
authored
May 04, 2018
by
Dimitris Lampridis
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Add new option to drive unsused register bits to zero instead of X
parent
9acf1cd6
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5 changed files
with
122 additions
and
102 deletions
+122
-102
target_pipelined_wb.lua
target_pipelined_wb.lua
+1
-1
target_wishbone.lua
target_wishbone.lua
+1
-1
wbgen2
wbgen2
+106
-96
wbgen_main.lua
wbgen_main.lua
+6
-1
wbgen_regbank.lua
wbgen_regbank.lua
+8
-3
No files found.
target_pipelined_wb.lua
View file @
6b6a3b7e
...
@@ -105,7 +105,7 @@ function gen_bus_logic_pipelined_wb(mode)
...
@@ -105,7 +105,7 @@ function gen_bus_logic_pipelined_wb(mode)
foreach_subfield
(
reg
,
function
(
field
,
reg
)
table_join
(
wcode
,
field
.
write_code
);
end
);
foreach_subfield
(
reg
,
function
(
field
,
reg
)
table_join
(
wcode
,
field
.
write_code
);
end
);
foreach_subfield
(
reg
,
function
(
field
,
reg
)
table_join
(
rcode
,
field
.
read_code
);
end
);
foreach_subfield
(
reg
,
function
(
field
,
reg
)
table_join
(
rcode
,
field
.
read_code
);
end
);
local
padcode
=
fill_unused_bits
(
"rddata_reg"
,
reg
);
local
padcode
=
fill_unused_bits
(
"rddata_reg"
,
reg
,
options
.
unused_zeroes
);
table_join
(
wcode
,
reg
.
write_code
);
table_join
(
wcode
,
reg
.
write_code
);
...
...
target_wishbone.lua
View file @
6b6a3b7e
...
@@ -98,7 +98,7 @@ function gen_bus_logic_wishbone()
...
@@ -98,7 +98,7 @@ function gen_bus_logic_wishbone()
foreach_subfield
(
reg
,
function
(
field
,
reg
)
table_join
(
wcode
,
field
.
write_code
);
end
);
foreach_subfield
(
reg
,
function
(
field
,
reg
)
table_join
(
wcode
,
field
.
write_code
);
end
);
foreach_subfield
(
reg
,
function
(
field
,
reg
)
table_join
(
rcode
,
field
.
read_code
);
end
);
foreach_subfield
(
reg
,
function
(
field
,
reg
)
table_join
(
rcode
,
field
.
read_code
);
end
);
local
padcode
=
fill_unused_bits
(
"rddata_reg"
,
reg
);
local
padcode
=
fill_unused_bits
(
"rddata_reg"
,
reg
,
options
.
unused_zeroes
);
table_join
(
wcode
,
reg
.
write_code
);
table_join
(
wcode
,
reg
.
write_code
);
...
...
wbgen2
View file @
6b6a3b7e
This diff is collapsed.
Click to expand it.
wbgen_main.lua
View file @
6b6a3b7e
...
@@ -28,6 +28,7 @@ options.lang = "vhdl";
...
@@ -28,6 +28,7 @@ options.lang = "vhdl";
options
.
c_reg_style
=
"struct"
;
options
.
c_reg_style
=
"struct"
;
options
.
hdl_reg_style
=
"signals"
;
options
.
hdl_reg_style
=
"signals"
;
options
.
doc_format
=
"html"
options
.
doc_format
=
"html"
options
.
unused_zeroes
=
false
require
"alt_getopt"
require
"alt_getopt"
...
@@ -50,6 +51,7 @@ local commands_string = [[options:
...
@@ -50,6 +51,7 @@ local commands_string = [[options:
-V, --vo=FILE Write the slave's generated HDL code to FILE
-V, --vo=FILE Write the slave's generated HDL code to FILE
-p, --vpo=FILE Generate a VHDL package for slave's generated VHDL
-p, --vpo=FILE Generate a VHDL package for slave's generated VHDL
(necessary with --hstyle=record)
(necessary with --hstyle=record)
-Z, --zeroes Drive unused register bits to '0' instead of 'X'
wbgen2 (c) Tomasz Wlostowski/CERN BE-CO-HT 2010-2012]]
wbgen2 (c) Tomasz Wlostowski/CERN BE-CO-HT 2010-2012]]
...
@@ -75,13 +77,14 @@ function parse_args(arg)
...
@@ -75,13 +77,14 @@ function parse_args(arg)
vo
=
"V"
,
vo
=
"V"
,
vpo
=
"p"
,
vpo
=
"p"
,
cstyle
=
"s"
,
cstyle
=
"s"
,
zeroes
=
"Z"
,
hstyle
=
"H"
hstyle
=
"H"
}
}
local
optarg
local
optarg
local
optind
local
optind
optarg
,
optind
=
alt_getopt
.
get_opts
(
arg
,
"hvC:D:K:l:V:s:f:H:p:"
,
long_opts
)
optarg
,
optind
=
alt_getopt
.
get_opts
(
arg
,
"hvC:D:K:l:V:s:f:H:p:
Z
"
,
long_opts
)
for
key
,
value
in
pairs
(
optarg
)
do
for
key
,
value
in
pairs
(
optarg
)
do
if
key
==
"h"
then
if
key
==
"h"
then
usage_complete
()
usage_complete
()
...
@@ -119,6 +122,8 @@ function parse_args(arg)
...
@@ -119,6 +122,8 @@ function parse_args(arg)
options
.
output_hdl_file
=
value
options
.
output_hdl_file
=
value
elseif
key
==
"p"
then
elseif
key
==
"p"
then
options
.
output_package_file
=
value
options
.
output_package_file
=
value
elseif
key
==
"Z"
then
options
.
unused_zeroes
=
true
elseif
key
==
"H"
then
elseif
key
==
"H"
then
if
(
value
~=
"signals"
and
value
~=
"record"
and
value
~=
"record_full"
)
then
if
(
value
~=
"signals"
and
value
~=
"record"
and
value
~=
"record_full"
)
then
die
(
"Unknown register style: "
..
value
);
die
(
"Unknown register style: "
..
value
);
...
...
wbgen_regbank.lua
View file @
6b6a3b7e
...
@@ -653,7 +653,7 @@ function gen_hdl_code_constant(field, reg)
...
@@ -653,7 +653,7 @@ function gen_hdl_code_constant(field, reg)
end
end
-- generates code which loads data unused bits of data output register with Xs
-- generates code which loads data unused bits of data output register with Xs
function
fill_unused_bits
(
target
,
reg
)
function
fill_unused_bits
(
target
,
reg
,
unused_zeroes
)
local
t
=
{};
local
t
=
{};
local
code
=
{};
local
code
=
{};
local
all_wo
=
true
;
local
all_wo
=
true
;
...
@@ -668,16 +668,21 @@ function fill_unused_bits(target, reg)
...
@@ -668,16 +668,21 @@ function fill_unused_bits(target, reg)
if
(
field
.
access_bus
~=
WRITE_ONLY
)
then
all_wo
=
false
;
end
if
(
field
.
access_bus
~=
WRITE_ONLY
)
then
all_wo
=
false
;
end
end
);
end
);
if
(
unused_zeroes
)
then
unused
=
0
;
else
unused
=
vundefined
();
end
if
(
all_wo
)
then
if
(
all_wo
)
then
for
i
=
0
,
DATA_BUS_WIDTH
-
1
do
for
i
=
0
,
DATA_BUS_WIDTH
-
1
do
table_join
(
code
,
{
va
(
vi
(
target
,
i
),
vundefined
()
);
});
table_join
(
code
,
{
va
(
vi
(
target
,
i
),
unused
);
});
end
end
return
code
;
return
code
;
end
end
for
i
=
0
,
DATA_BUS_WIDTH
-
1
do
for
i
=
0
,
DATA_BUS_WIDTH
-
1
do
if
(
t
[
i
]
==
nil
)
then
if
(
t
[
i
]
==
nil
)
then
table_join
(
code
,
{
va
(
vi
(
target
,
i
),
vundefined
()
);
});
table_join
(
code
,
{
va
(
vi
(
target
,
i
),
unused
);
});
end
end
end
end
...
...
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