Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
W
Wishbone slave generator
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
24
Issues
24
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Wishbone slave generator
Commits
7f405392
Commit
7f405392
authored
Sep 09, 2013
by
Grzegorz Daniluk
Committed by
Tomasz Wlostowski
Sep 09, 2013
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
cgen_doc_latex: print SW Offset instead of HW Addr in Memory Map Summary
parent
8fbd2914
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
6 additions
and
6 deletions
+6
-6
cgen_doc_latex.lua
cgen_doc_latex.lua
+3
-3
wbgen2
wbgen2
+3
-3
No files found.
cgen_doc_latex.lua
View file @
7f405392
...
...
@@ -69,12 +69,12 @@ function cgen_doc_lx_memmap()
emit
(
'
\\
resizebox{\\textwidth}{!}{'
);
emit
(
'
\\
begin{tabular}{|l|l|l|l|l|}'
);
emit
(
'
\\
rowcolor{RoyalPurple}'
);
emit
(
'
\\
color{white}
H/W Addr
& \\color{white} Type & \\color{white} Name &'
);
emit
(
'
\\
color{white}
SW Offset
& \\color{white} Type & \\color{white} Name &'
);
emit
(
'
\\
color{white} HW prefix & \\color{white} C prefix\\\\'
);
foreach_reg
({
TYPE_REG
},
function
(
reg
)
if
(
reg
.
full_hdl_prefix
~=
nil
)
then
reg_text
=
string.format
(
"0x%x"
,
reg
.
base
)
..
'& '
;
reg_text
=
string.format
(
"0x%x"
,
reg
.
base
*
(
DATA_BUS_WIDTH
/
8
)
)
..
'& '
;
if
(
reg
.
doc_is_fiforeg
==
nil
)
then
reg_text
=
reg_text
..
"REG & "
;
...
...
@@ -91,7 +91,7 @@ function cgen_doc_lx_memmap()
foreach_reg
({
TYPE_RAM
},
function
(
reg
)
if
(
reg
.
full_hdl_prefix
~=
nil
)
then
reg_text
=
string.format
(
"0x%x - 0x%x"
,
reg
.
base
,
reg
.
base
+
math.pow
(
2
,
reg
.
wrap_bits
)
*
reg
.
size
-
1
)
..
'& '
;
reg_text
=
string.format
(
"0x%x - 0x%x"
,
reg
.
base
*
(
DATA_BUS_WIDTH
/
8
),
reg
.
base
*
(
DATA_BUS_WIDTH
/
8
)
+
(
math.pow
(
2
,
reg
.
wrap_bits
)
*
reg
.
size
-
1
)
*
DATA_BUS_WIDTH
/
8
)
..
'& '
;
reg_text
=
reg_text
..
"MEM & "
..
reg
.
name
..
" & "
..
reg
.
full_hdl_prefix
..
" & "
..
string.upper
(
reg
.
c_prefix
)
..
"
\\\\
"
;
reg_text
=
string.gsub
(
reg_text
,
"_"
,
"
\\
_"
);
...
...
wbgen2
View file @
7f405392
...
...
@@ -2590,11 +2590,11 @@ emit('\\rowcolors{2}{gray!25}{white}');
emit
(
'
\\
resizebox{\\textwidth}{!}{'
);
emit
(
'
\\
begin{tabular}{|l|l|l|l|l|}'
);
emit
(
'
\\
rowcolor{RoyalPurple}'
);
emit
(
'
\\
color{white}
H/W Addr
& \\color{white} Type & \\color{white} Name &'
);
emit
(
'
\\
color{white}
SW Offset
& \\color{white} Type & \\color{white} Name &'
);
emit
(
'
\\
color{white} HW prefix & \\color{white} C prefix\\\\'
);
foreach_reg
({
TYPE_REG
},
function
(
t
)
if
(
t
.
full_hdl_prefix
~=
nil
)
then
e
=
string.format
(
"0x%x"
,
t
.
base
)
..
'& '
;
e
=
string.format
(
"0x%x"
,
t
.
base
*
(
DATA_BUS_WIDTH
/
8
)
)
..
'& '
;
if
(
t
.
doc_is_fiforeg
==
nil
)
then
e
=
e
..
"REG & "
;
else
...
...
@@ -2607,7 +2607,7 @@ end
end
);
foreach_reg
({
TYPE_RAM
},
function
(
t
)
if
(
t
.
full_hdl_prefix
~=
nil
)
then
e
=
string.format
(
"0x%x - 0x%x"
,
t
.
base
,
t
.
base
+
math.pow
(
2
,
t
.
wrap_bits
)
*
t
.
size
-
1
)
..
'& '
;
e
=
string.format
(
"0x%x - 0x%x"
,
t
.
base
*
(
DATA_BUS_WIDTH
/
8
),
t
.
base
*
(
DATA_BUS_WIDTH
/
8
)
+
(
math.pow
(
2
,
t
.
wrap_bits
)
*
t
.
size
-
1
)
*
DATA_BUS_WIDTH
/
8
)
..
'& '
;
e
=
e
..
"MEM & "
..
t
.
name
..
" & "
..
t
.
full_hdl_prefix
..
" & "
..
string.upper
(
t
.
c_prefix
)
..
"
\\\\
"
;
e
=
string.gsub
(
e
,
"_"
,
"
\\
_"
);
emit
(
e
);
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment