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Wishbone slave generator
Commit 7f478544 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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updated squished binary

parent f4b155be
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Showing with 370 additions and 306 deletions
wbgen2
View file @ 7f478544
#!/usr/bin/env lua
package.preload['alt_getopt']=(function(...)
local o,d,u,a,i=type,pairs,ipairs,io,os
local n,r,u,a,o=type,pairs,ipairs,io,os
module("alt_getopt")
local function c(t)
local function i(t)
local e=1
local e=#t
local e={}
......@@ -11,19 +11,19 @@ e[a]=#t
end
return e
end
local function r(t,e)
local function d(t,e)
a.stderr:write(t)
i.exit(e)
o.exit(e)
end
local function a(e)
r("Unknown option `-"..
d("Unknown option `-"..
(#e>1 and"-"or"")..e.."'\n",1)
end
local function l(t,e)
if not t[e]then
a(e)
end
while o(t[e])=="string"do
while n(t[e])=="string"do
e=t[e]
if not t[e]then
a(e)
......@@ -34,11 +34,11 @@ end
function get_ordered_opts(n,a,s)
local t=1
local e=1
local i={}
local o={}
local h={}
local o=c(a)
for e,t in d(s)do
o[e]=t
local i=i(a)
for t,e in r(s)do
i[t]=e
end
while t<=#n do
local a=n[t]
......@@ -51,46 +51,46 @@ elseif a:sub(1,2)=="--"then
local s=a:find("=",1,true)
if s then
local t=a:sub(3,s-1)
t=l(o,t)
if o[t]==0 then
r("Bad usage of option `"..a.."'\n",1)
t=l(i,t)
if i[t]==0 then
d("Bad usage of option `"..a.."'\n",1)
end
h[e]=a:sub(s+1)
i[e]=t
o[e]=t
else
local s=a:sub(3)
s=l(o,s)
if o[s]==0 then
i[e]=s
s=l(i,s)
if i[s]==0 then
o[e]=s
else
if t==#n then
r("Missed value for option `"..a.."'\n",1)
d("Missed value for option `"..a.."'\n",1)
end
h[e]=n[t+1]
i[e]=s
o[e]=s
t=t+1
end
end
e=e+1
elseif a:sub(1,1)=="-"then
local s
for d=2,a:len()do
local s=l(o,a:sub(d,d))
if o[s]==0 then
i[e]=s
for r=2,a:len()do
local s=l(i,a:sub(r,r))
if i[s]==0 then
o[e]=s
e=e+1
elseif a:len()==d then
elseif a:len()==r then
if t==#n then
r("Missed value for option `-"..s.."'\n",1)
d("Missed value for option `-"..s.."'\n",1)
end
h[e]=n[t+1]
i[e]=s
o[e]=s
t=t+1
e=e+1
break
else
h[e]=a:sub(d+1)
i[e]=s
h[e]=a:sub(r+1)
o[e]=s
e=e+1
break
end
......@@ -100,16 +100,16 @@ break
end
t=t+1
end
return i,t,h
return o,t,h
end
function get_opts(a,t,o)
function get_opts(t,o,a)
local e={}
local t,i,o=get_ordered_opts(a,t,o)
for t,a in u(t)do
if o[t]then
e[a]=o[t]
local a,i,t=get_ordered_opts(t,o,a)
for a,o in u(a)do
if t[a]then
e[o]=t[a]
else
e[a]=1
e[o]=1
end
end
return e,i
......@@ -176,22 +176,22 @@ die(t.." expected.");
end
return e;
end
function range2bits(t)
local e=t[1];
local a=t[2];
local t;
if(math.abs(e)>math.abs(a))then
t=math.abs(e);
function range2bits(e)
local t=e[1];
local a=e[2];
local e;
if(math.abs(t)>math.abs(a))then
e=math.abs(t);
else
t=math.abs(a);
e=math.abs(a);
end
local t=math.ceil(math.log(t)/math.log(2));
if(e<0)then
t=t+1;
local e=math.ceil(math.log(e)/math.log(2));
if(t<0)then
e=e+1;
end
return t;
return e;
end
function calc_size(e,a)
function calc_size(e,t)
if(e.type==MONOSTABLE or e.type==BIT)then
e.size=1;
elseif(e.type==SLV or e.type==PASS_THROUGH)then
......@@ -212,7 +212,7 @@ end
elseif(e.type==ENUM)then
die("ENUM-type fields are not yet supported. Sorry :(");
end
a.total_size=a.total_size+e.size;
t.total_size=t.total_size+e.size;
end
function foreach_reg(t,a,e)
if(e==nil)then
......@@ -286,15 +286,15 @@ if(t==e)then return true;end
end
return false;
end
function inset(e,t)
for a,t in ipairs(t)do if(e==t)then return true;end end
function inset(t,e)
for a,e in ipairs(e)do if(t==e)then return true;end end
return false;
end
function csel(a,e,t)
if(a)then
return e;
else
function csel(e,t,a)
if(e)then
return t;
else
return a;
end
end
function check_field_types(e)
......@@ -318,13 +318,13 @@ return e;
end
return e;
end
function default_access(e,o,a,t)
if(e.type==o)then
function default_access(e,a,t,o)
if(e.type==a)then
if(e.access_bus==nil)then
e.access_bus=a;
e.access_bus=t;
end
if(e.access_dev==nil)then
e.access_dev=t;
e.access_dev=o;
end
end
end
......@@ -412,11 +412,11 @@ end);
address_bus_width=o+a;
address_bus_select_bits=a;
end
function find_max(e,a)
local t=0;
function find_max(e,t)
local a=0;
local o,o;
for o,e in pairs(e)do if(type(e)=='table'and e[a]~=nil and e[a]>t)then t=e[a];end end
return t;
for o,e in pairs(e)do if(type(e)=='table'and e[t]~=nil and e[t]>a)then a=e[t];end end
return a;
end
function table_join(t,e)
local a,a;
......@@ -426,32 +426,32 @@ table.insert(t,e);
end
end
function tree_2_table(e)
local t={};
foreach_reg({TYPE_REG,TYPE_RAM,TYPE_FIFO,TYPE_IRQ},function(a)
if(a[e]~=nil)then
if(type(a[e])=='table')then
table_join(t,a[e]);
local a={};
foreach_reg({TYPE_REG,TYPE_RAM,TYPE_FIFO,TYPE_IRQ},function(t)
if(t[e]~=nil)then
if(type(t[e])=='table')then
table_join(a,t[e]);
else
table.insert(t,a[e]);
table.insert(a,t[e]);
end
end
foreach_subfield(a,function(a,o)
if(a[e]~=nil)then
if(type(a[e])=='table')then
table_join(t,a[e]);
foreach_subfield(t,function(t,o)
if(t[e]~=nil)then
if(type(t[e])=='table')then
table_join(a,t[e]);
else
table.insert(t,a[e]);
table.insert(a,t[e]);
end
end
end);
end);
return t;
return a;
end
function remove_duplicates(a)
function count_entries(a,t)
function count_entries(t,a)
local o,o,e;
e=0;
for o,a in ipairs(a)do if(a==t)then e=e+1;end end
for o,t in ipairs(t)do if(t==a)then e=e+1;end end
return e;
end
local e={};
......@@ -465,37 +465,37 @@ return e;
end
function wbgen_count_subblocks()
local o=0;
local t=0;
local a=0;
local e=0;
local t=0;
foreach_reg({TYPE_RAM},function(e)o=o+1;end);
foreach_reg({TYPE_REG},function(t)e=e+1;end);
foreach_reg({TYPE_FIFO},function(e)a=a+1;end);
foreach_reg({TYPE_IRQ},function(e)t=t+1;end);
foreach_reg({TYPE_REG},function(e)a=a+1;end);
foreach_reg({TYPE_FIFO},function(e)t=t+1;end);
foreach_reg({TYPE_IRQ},function(t)e=e+1;end);
periph.ramcount=o;
periph.fifocount=a;
periph.regcount=e;
periph.irqcount=t;
if(o+a+e+t==0)then
periph.fifocount=t;
periph.regcount=a;
periph.irqcount=e;
if(o+t+a+e==0)then
die("Can't generate an empty peripheral. Define some regs, RAMs, FIFOs or IRQs, please...");
end
end
function deepcopy(i)
local o={}
local function a(e)
local function t(e)
if type(e)~="table"then
return e
elseif o[e]then
return o[e]
end
local t={}
o[e]=t
for e,o in pairs(e)do
t[a(e)]=a(o)
local a={}
o[e]=a
for o,e in pairs(e)do
a[t(o)]=t(e)
end
return setmetatable(t,getmetatable(e))
return setmetatable(a,getmetatable(e))
end
return a(i)
return t(i)
end
function va(a,t)
local e={};
......@@ -504,27 +504,27 @@ e.dst=a;
e.src=t;
return e;
end
function vi(o,t,a)
function vi(t,a,o)
local e={};
e.t="index";
e.name=o;
e.h=t;
e.l=a;
e.name=t;
e.h=a;
e.l=o;
return e;
end
function vinstance(t,a,o)
function vinstance(t,o,a)
local e={};
e.t="instance";
e.name=t;
e.component=a;
e.maps=o;
e.component=o;
e.maps=a;
return e;
end
function vpm(a,t)
function vpm(t,a)
local e={};
e.t="portmap";
e.to=a;
e.from=t;
e.to=t;
e.from=a;
return e;
end
function vgm(t,a)
......@@ -541,19 +541,19 @@ e.slist=t;
e.code=a;
return e;
end
function vsyncprocess(a,t,o)
function vsyncprocess(o,a,t)
local e={};
e.t="syncprocess";
e.clk=a;
e.rst=t;
e.code=o;
e.clk=o;
e.rst=a;
e.code=t;
return e;
end
function vreset(a,t)
function vreset(t,a)
local e={};
e.t="reset";
e.level=a;
e.code=t;
e.level=t;
e.code=a;
return e;
end
function vposedge(t)
......@@ -570,6 +570,13 @@ e.code=a;
e.code_else=o;
return e;
end
function vgenerate_if(a,t)
local e={};
e.t="generate_if";
e.cond={a};
e.code=t;
return e;
end
function vequal(a,t)
local e={};
e.t="eq";
......@@ -597,18 +604,18 @@ e.t="not";
e.a=t;
return e;
end
function vswitch(t,a)
function vswitch(a,t)
local e={};
e.t="switch";
e.a=t;
e.code=a;
e.a=a;
e.code=t;
return e;
end
function vcase(a,t)
function vcase(t,a)
local e={};
e.t="case";
e.a=a;
e.code=t;
e.a=t;
e.code=a;
return e;
end
function vcasedefault(t)
......@@ -623,11 +630,11 @@ e.t="comment";
e.str=t;
return e;
end
function vsub(t,a)
function vsub(a,t)
local e={};
e.t="sub";
e.a=t;
e.b=a;
e.a=a;
e.b=t;
return e;
end
function vothers(t)
......@@ -646,23 +653,23 @@ local e={}
e.t="undefined";
return e;
end
function signal(t,o,a,i)
function signal(t,a,o,i)
local e={}
e.comment=i;
e.type=t;
e.range=o;
e.name=a;
e.range=a;
e.name=o;
return e;
end
VPORT_WB=1;
VPORT_REG=2;
function port(a,n,s,i,o,t)
function port(a,i,o,n,s,t)
local e={}
e.comment=o;
e.comment=s;
e.type=a;
e.range=n;
e.name=i;
e.dir=s;
e.range=i;
e.name=n;
e.dir=o;
if(t~=nil)then
if(t==VPORT_WB)then
e.is_wb=true;
......@@ -713,15 +720,35 @@ table_join(e,cgen_build_clock_list());
table_join(e,tree_2_table("ports"));
return e;
end
function cgen_build_optional_list()
local a={}
local o={}
local e=1
for i,t in pairs(tree_2_table("optional"))do
if a[t]==nil then
a[t]=1
o[e]=t
e=e+1
end
end
return o
end
function cgen_find_sigport(e)
for a,t in pairs(g_portlist)do if(e==t.name)then return t;end end
for a,t in pairs(g_siglist)do if(e==t.name)then return t;end end
for a,t in pairs(g_optlist)do if(e==t)then
local e={}
e.type=INTEGER;
e.name=t;
return e;
end end
die("cgen internal error: undefined signal '"..e.."'");
return nil;
end
function cgen_build_signals_ports()
g_portlist=cgen_build_portlist();
g_siglist=cgen_build_siglist();
g_optlist=cgen_build_optional_list();
end
cur_indent=0;
function indent_zero()
......@@ -799,23 +826,23 @@ function gen_vhdl_bin_literal(i,a)
if(a==1)then
return string.format("'%d'",csel(i==0,0,1));
end
local t='\"';
local s,o,n,e;
local e='\"';
local s,o,n,t;
o=i;
e=math.pow(2,a-1);
t=math.pow(2,a-1);
if(i==nil)then
for e=1,a do
t=t.."X";
for t=1,a do
e=e.."X";
end
else
for a=1,a do
n=math.floor(o/e);
t=t..csel(n>0,"1","0");
o=o%e;
e=e/2;
n=math.floor(o/t);
e=e..csel(n>0,"1","0");
o=o%t;
t=t/2;
end
end
return t..'\"';
return e..'\"';
end
function strip_periph_prefix(e)
return string.gsub(e,"^"..periph.hdl_prefix.."\_","")
......@@ -956,6 +983,23 @@ emit("\n");
end
emit("entity "..periph.hdl_entity.." is");
indent_right();
if(table.getn(g_optlist)~=0)then
emit("generic (");
indent_right();
emiti()
for t,e in pairs(g_optlist)do
emiti();
emitx(e.." : integer := 1");
if(t~=table.getn(g_optlist))then
emit(";")
else
emit(");")
end
end
indent_left();
end
indent_left();
indent_right();
emit("port (");
indent_right();
for a=1,table.getn(g_portlist)do
......@@ -964,7 +1008,6 @@ if(options.hdl_reg_style=="signals"or not e.is_reg_port)then
if(e.comment~=nil and e.comment~="")then
emitx("-- "..e.comment.."\n");
end
print(e.name.." "..e.type)
local t=string.format("%-40s : %-6s %s",e.name,e.dir,fieldtype_2_vhdl[e.type]);
if(e.range>1 or e.type==SLV)then
t=t.."("..(e.range-1).." downto 0)";
......@@ -1049,22 +1092,22 @@ emit("end process;");
emit("");
emit("");
end
function cgen_vhdl_combprocess(e)
local t=true;
function cgen_vhdl_combprocess(t)
local e=true;
emiti();
emitx("process (");
for a,e in pairs(e.slist)do
if(t)then
t=false;
for a,t in pairs(t.slist)do
if(e)then
e=false;
else
emitx(", ");
end
emitx(e);
emitx(t);
end
emit(")");
emit("begin");
indent_right();
recurse(e.code);
recurse(t.code);
indent_left();
emit("end process;");
emit("");
......@@ -1194,13 +1237,26 @@ indent_right();recurse(e.code);indent_left();
emit("end if;");
end
end
function cgen_vhdl_not(t)
local e=node_typesize(t.a);
function cgen_vhdl_generate_if(e)
if(g_gen_block_count==nil)then
g_gen_block_count=0
else
g_gen_block_count=g_gen_block_count+1
end
gname=string.format("genblock_%d",g_gen_block_count)
emiti();emitx(gname..": if (");
recurse(e.cond);
emitx(") generate\n");
indent_right();recurse(e.code);indent_left();
emit("end generate "..gname..";");
end
function cgen_vhdl_not(e)
local t=node_typesize(e.a);
emitx("not ");
if(e.type==EXPRESSION)then
emitx("(");recurse({t.a});emitx(")");
if(t.type==EXPRESSION)then
emitx("(");recurse({e.a});emitx(")");
else
emitx(gen_subrange(e));
emitx(gen_subrange(t));
end
end
function cgen_vhdl_binary_op(t)
......@@ -1253,25 +1309,25 @@ end
emit("end case;");
end
function cgen_vhdl_instance(t)
local a=0;
local o=0;
local a=0;
local e;
emit(t.name.." : "..t.component);
for t,e in pairs(t.maps)do
if(e.t=="genmap")then
o=o+1;
elseif(e.t=="portmap")then
a=a+1;
elseif(e.t=="portmap")then
o=o+1;
end
end
if(o>0)then
if(a>0)then
indent_right();
emit("generic map (");
indent_right();
e=1;
for a,t in pairs(t.maps)do
for o,t in pairs(t.maps)do
if(t.t=="genmap")then
emit(string.format("%-20s => %s",t.to,t.from)..csel(e==o,"",","));
emit(string.format("%-20s => %s",t.to,t.from)..csel(e==a,"",","));
e=e+1;
end
end
......@@ -1279,15 +1335,15 @@ indent_left();
emit(")");
indent_left();
end
if(a>0)then
if(o>0)then
indent_right();
emit("port map (");
indent_right();
e=1;
for o,t in pairs(t.maps)do
for a,t in pairs(t.maps)do
if(t.t=="portmap")then
local o=node_typesize(t.from);
emit(string.format("%-20s => %s",t.to,gen_subrange(o))..csel(e==a,"",","));
local a=node_typesize(t.from);
emit(string.format("%-20s => %s",t.to,gen_subrange(a))..csel(e==o,"",","));
e=e+1;
end
end
......@@ -1310,6 +1366,7 @@ local t={
["combprocess"]=cgen_vhdl_combprocess;
["assign"]=cgen_vhdl_assign;
["if"]=cgen_vhdl_if;
["generate_if"]=cgen_vhdl_generate_if;
["eq"]=cgen_vhdl_binary_op;
["add"]=cgen_vhdl_binary_op;
["sub"]=cgen_vhdl_binary_op;
......@@ -1419,7 +1476,7 @@ function cgen_verilog_ending()
indent_left();
emit("endmodule");
end
function cgen_generate_verilog_code(n)
function cgen_generate_verilog_code(i)
local a=false;
function find_code(e,t)
for a,e in ipairs(e)do if((e.t~=nil)and(e.t==t))then return e;end end
......@@ -1566,13 +1623,13 @@ indent_left();
emit("end");
end
end
function cgen_verilog_not(t)
local e=node_typesize(t.a);
function cgen_verilog_not(e)
local t=node_typesize(e.a);
emitx("! ");
if(e.type==EXPRESSION)then
emitx("(");recurse({t.a});emitx(")");
if(t.type==EXPRESSION)then
emitx("(");recurse({e.a});emitx(")");
else
emitx(gen_subrange(e));
emitx(gen_subrange(t));
end
end
function cgen_verilog_binary_op(e)
......@@ -1624,29 +1681,29 @@ end
end
emit("endcase");
end
function cgen_verilog_instance(a)
function cgen_verilog_instance(t)
local a=0;
local o=0;
local i=0;
local e;
emitx(a.component.." ");
for t,e in pairs(a.maps)do
emitx(t.component.." ");
for t,e in pairs(t.maps)do
if(e.t=="genmap")then
i=i+1;
elseif(e.t=="portmap")then
o=o+1;
elseif(e.t=="portmap")then
a=a+1;
end
end
if(i>0)then
if(o>0)then
indent_right();
emit("# (");
indent_right();
e=1;
for t,a in pairs(a.maps)do
for t,a in pairs(t.maps)do
if(a.t=="genmap")then
local t=a.from;
if(t=="true")then t=1;
elseif(t=="false")then t=0;end
emit(string.format(".%-20s(%s)",a.to,t)..csel(e==i,"",","));
emit(string.format(".%-20s(%s)",a.to,t)..csel(e==o,"",","));
e=e+1;
end
end
......@@ -1654,15 +1711,15 @@ indent_left();
emit(")");
indent_left();
end
if(o>0)then
if(a>0)then
indent_right();
emit(a.name.." ( ");
emit(t.name.." ( ");
indent_right();
e=1;
for a,t in pairs(a.maps)do
for o,t in pairs(t.maps)do
if(t.t=="portmap")then
local a=node_typesize(t.from);
emit(string.format(".%-20s(%s)",t.to,gen_subrange(a))..csel(e==o,"",","));
local o=node_typesize(t.from);
emit(string.format(".%-20s(%s)",t.to,gen_subrange(o))..csel(e==a,"",","));
e=e+1;
end
end
......@@ -1729,17 +1786,17 @@ end
end
cgen_new_snippet();
cgen_verilog_header();
local a=cgen_get_snippet();
local e=cgen_get_snippet();
cgen_new_snippet();
recurse(n);
recurse(i);
cgen_verilog_ending();
local t=cgen_get_snippet();
local a=cgen_get_snippet();
cgen_new_snippet();
cgen_verilog_module();
local e=cgen_get_snippet();
cgen_write_snippet(a);
local t=cgen_get_snippet();
cgen_write_snippet(e);
cgen_write_snippet(t);
cgen_write_snippet(a);
end
function cgen_c_field_define(e,a)
local t;
......@@ -1776,7 +1833,7 @@ dbg("DOCREG: ",e.name,e.num_fields);
if(e.num_fields~=nil and e.num_fields>0)then
emit("");
emit("/* definitions for register: "..e.name.." */");
foreach_subfield(e,function(e,t)cgen_c_field_define(e,t)end);
foreach_subfield(e,function(t,e)cgen_c_field_define(t,e)end);
end
end);
foreach_reg({TYPE_RAM},function(e)
......@@ -1912,21 +1969,21 @@ end
end
return e;
end
function htable_tdstyle(a,t,e)
tbl.data[a][t].style=e;
function htable_tdstyle(e,a,t)
tbl.data[e][a].style=t;
end
function htable_trstyle(e,a,t)
tbl.data[e].style=t;
function htable_trstyle(t,a,e)
tbl.data[t].style=e;
end
function htable_frame(e,t,o,a)
if(a==nil)then
e.data[t][o].extra='style="border: solid 1px black;"';
function htable_frame(a,o,t,e)
if(e==nil)then
a.data[o][t].extra='style="border: solid 1px black;"';
else
e.data[t][o].extra='style="border-left: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
e.data[t][a].extra='style="border-right: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
if(a>o+1)then
for a=o+1,a-1 do
e.data[t][a].extra='border-top: solid 1px black; border-bottom: solid 1px black;';
a.data[o][t].extra='style="border-left: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
a.data[o][e].extra='style="border-right: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
if(e>t+1)then
for e=t+1,e-1 do
a.data[o][e].extra='border-top: solid 1px black; border-bottom: solid 1px black;';
end
end
end
......@@ -1964,11 +2021,11 @@ emit("</tr>");
end
emit("</table>");
end
function has_any_ports(t)
local e=false;
if(t.ports~=nil)then return true;end
foreach_subfield(t,function(t)if(t.ports~=nil)then e=true;end end);
return e;
function has_any_ports(e)
local t=false;
if(e.ports~=nil)then return true;end
foreach_subfield(e,function(e)if(e.ports~=nil)then t=true;end end);
return t;
end
function htable_add_row(e,a)
if(a>e.rows)then
......@@ -1982,27 +2039,27 @@ end
e.rows=a;
end
end
function hlink(t,e)
return'<A href="'..t..'">'..e..'</a>';
function hlink(e,t)
return'<A href="'..e..'">'..t..'</a>';
end
function hitem(e)
return'<li>'..e..'</li>';
end
function hanchor(t,e)
return'<a name="'..t..'">'..e..'</a>';
function hanchor(e,t)
return'<a name="'..e..'">'..t..'</a>';
end
doc_toc={};
function hsection(t,a,o)
function hsection(a,t,o)
local e={};
local i=0;
e.id_mangled="sect_"..t.."_"..a;
e.key=t*1e3+a;
if(a~=0)then
e.id_mangled="sect_"..a.."_"..t;
e.key=a*1e3+t;
if(t~=0)then
e.level=2;
e.id=t.."."..a..".";
e.id=a.."."..t..".";
else
e.level=1;
e.id=t..".";
e.id=a..".";
end
e.name=o;
table.insert(doc_toc,e);
......@@ -2051,23 +2108,23 @@ end
end);
cgen_doc_symbol(t);
end
function cgen_doc_mem_symbol(a)
local t={};
for e,a in pairs(a.ports)do
local e=a;
if(string.find(a.name,"_i")~=nil)then
function cgen_doc_mem_symbol(t)
local a={};
for e,t in pairs(t.ports)do
local e=t;
if(string.find(t.name,"_i")~=nil)then
e.is_wb=true;
else
e.is_wb=false;
end
table.insert(t,e);
table.insert(a,e);
end
if(a.clock~=nil)then
local e=port(BIT,0,"in",a.clock);
if(t.clock~=nil)then
local e=port(BIT,0,"in",t.clock);
e.is_wb=true;
table.insert(t,e);
table.insert(a,e);
end
cgen_doc_symbol(t);
cgen_doc_symbol(a);
end
function cgen_doc_symbol(i)
local t=htable_new(3,5);
......@@ -2125,7 +2182,7 @@ local e=periph.description;
if(e==nil)then e="";end
emit('<p>'..string.gsub(e,"\n","<br>")..'</p>');
emit('<h3>Contents:</h3>');
table.sort(doc_toc,function(t,e)return t.key<e.key;end);
table.sort(doc_toc,function(e,t)return e.key<t.key;end);
for t,e in ipairs(doc_toc)do
emit('<span style="margin-left: '..((e.level-1)*20)..'px; ">'..e.id.." "..hlink('#'..e.id_mangled,e.name)..'</span><br/>');
end
......@@ -2162,28 +2219,28 @@ e[5].text=string.upper(t.c_prefix);
i=not i;
end
end);
foreach_reg({TYPE_RAM},function(e)
if(e.full_hdl_prefix~=nil)then
foreach_reg({TYPE_RAM},function(t)
if(t.full_hdl_prefix~=nil)then
htable_add_row(o,a);
local t=o.data[a];a=a+1;
t.style=csel(i,"tr_odd","tr_even");
t[1].style="td_code";
t[1].text=string.format("0x%x - 0x%x",e.base,e.base+math.pow(2,e.wrap_bits)*e.size-1);
t[2].text="MEM";
t[3].text=hlink("#"..string.upper(e.c_prefix),e.name);
t[4].style="td_code";
t[4].text=e.full_hdl_prefix;
t[5].style="td_code";
t[5].text=string.upper(e.c_prefix);
local e=o.data[a];a=a+1;
e.style=csel(i,"tr_odd","tr_even");
e[1].style="td_code";
e[1].text=string.format("0x%x - 0x%x",t.base,t.base+math.pow(2,t.wrap_bits)*t.size-1);
e[2].text="MEM";
e[3].text=hlink("#"..string.upper(t.c_prefix),t.name);
e[4].style="td_code";
e[4].text=t.full_hdl_prefix;
e[5].style="td_code";
e[5].text=string.upper(t.c_prefix);
i=not i;
end
end);
htable_emit(o);
end
function find_field_by_offset(e,a)
local t=nil;
foreach_subfield(e,function(e)if(a>=e.offset and a<=(e.offset+e.size-1))then t=e;end end);
return t;
function find_field_by_offset(e,t)
local a=nil;
foreach_subfield(e,function(e)if(t>=e.offset and t<=(e.offset+e.size-1))then a=e;end end);
return a;
end
function cgen_doc_fieldtable(h,i)
local e=70;
......@@ -2344,25 +2401,25 @@ if(t.description~=nil)then
emit("<p>"..string.gsub(t.description,"\n","<br>").."</p>");
end
end
function cgen_generate_documentation()
function cgen_generate_html_documentation()
cgen_new_snippet();cgen_doc_hdl_symbol();local i=cgen_get_snippet();
cgen_new_snippet();
emit(hsection(3,0,"Register description"));
foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_reg(e);end end);
local o=cgen_get_snippet();
local t="";
local a="";
if(periph.ramcount>0)then
emit(hsection(4,0,"Memory blocks"));
cgen_new_snippet();
foreach_reg({TYPE_RAM},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_ram(e);end end);
t=cgen_get_snippet();
a=cgen_get_snippet();
end
local a="";
local t="";
if(periph.irqcount>0)then
cgen_new_snippet();
emit(hsection(5,0,"Interrupts"));
foreach_reg({TYPE_IRQ},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_irq(e);end end);
a=cgen_get_snippet();
t=cgen_get_snippet();
end
cgen_new_snippet();
cgen_doc_memmap();
......@@ -2372,8 +2429,8 @@ cgen_doc_header_and_toc();
emit(e);
emit(i);
emit(o);
emit(t);
emit(a);
emit(t);
emit('</BODY>');
emit('</HTML>');
cgen_write_current_snippet();
......@@ -3290,27 +3347,27 @@ e.ports={};
e.acklen=1;
e.read_code={va(vir("rddata_reg",e),e.value);};
end
function fill_unused_bits(i,e)
function fill_unused_bits(o,e)
local a={};
local t={};
local o=true;
local i=true;
foreach_subfield(e,function(e,t)
if(e.type==SLV or e.type==SIGNED or e.type==UNSIGNED or e.type==CONSTANT)then
for e=e.offset,(e.offset+e.size-1)do a[e]=1;end
elseif(e.type==BIT or e.type==MONOSTABLE)then
a[e.offset]=1;
end
if(e.access_bus~=WRITE_ONLY)then o=false;end
if(e.access_bus~=WRITE_ONLY)then i=false;end
end);
if(o)then
if(i)then
for e=0,DATA_BUS_WIDTH-1 do
table_join(t,{va(vi(i,e),vundefined());});
table_join(t,{va(vi(o,e),vundefined());});
end
return t;
end
for e=0,DATA_BUS_WIDTH-1 do
if(a[e]==nil)then
table_join(t,{va(vi(i,e),vundefined());});
table_join(t,{va(vi(o,e),vundefined());});
end
end
return t;
......@@ -3433,8 +3490,8 @@ end
function wbgen_generate_eic()
if(periph.irqcount==0)then return;end
local t=0;
local s={};
local i={["__type"]=TYPE_REG;
local a={};
local o={["__type"]=TYPE_REG;
["__blockindex"]=1e6;
["align"]=8;
["name"]="Interrupt disable register";
......@@ -3450,7 +3507,7 @@ signal(BIT,0,"eic_idr_write_int");};
["extra_code"]={va(vi("eic_idr_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true;
};
local a={["__type"]=TYPE_REG;
local i={["__type"]=TYPE_REG;
["__blockindex"]=1000001;
["align"]=1;
["name"]="Interrupt enable register";
......@@ -3466,7 +3523,7 @@ signal(BIT,0,"eic_ier_write_int");};
["extra_code"]={va(vi("eic_ier_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true;
};
local o={["__type"]=TYPE_REG;
local n={["__type"]=TYPE_REG;
["__blockindex"]=1000002;
["align"]=1;
["name"]="Interrupt status register";
......@@ -3485,7 +3542,7 @@ signal(BIT,0,"eic_isr_write_int");};
["extra_code"]={va(vi("eic_isr_clear_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true;
};
local n={["__type"]=TYPE_REG;
local s={["__type"]=TYPE_REG;
["__blockindex"]=1000003;
["align"]=1;
["name"]="Interrupt mask register";
......@@ -3500,7 +3557,7 @@ local n={["__type"]=TYPE_REG;
foreach_reg({TYPE_IRQ},function(e)
e.index=t;
t=t+1;
table.insert(s,{["index"]=e.index;["trigger"]=e.trigger;});
table.insert(a,{["index"]=e.index;["trigger"]=e.trigger;});
fix_prefix(e);
local t={
["__blockindex"]=e.index;
......@@ -3513,7 +3570,7 @@ local t={
["access_bus"]=READ_WRITE;
["access_dev"]=READ_WRITE;
};
local s={
local a={
["__blockindex"]=e.index;
["__type"]=TYPE_FIELD;
["type"]=BIT;
......@@ -3555,18 +3612,18 @@ end
if(e.mask_line==true)then
table_join(e.ports,{port(BIT,0,"out",e.full_prefix.."_mask_o");});
end
table.insert(i,r);
table.insert(o,t);
table.insert(n,h);
table.insert(a,s);
table.insert(o,r);
table.insert(n,t);
table.insert(s,h);
table.insert(i,a);
end);
add_global_signals({
signal(SLV,periph.irqcount,"irq_inputs_vector_int");
});
table.insert(periph,o);
table.insert(periph,i);
table.insert(periph,a);
table.insert(periph,s);
table.insert(periph,n);
table.insert(periph,o);
local e={vgm("g_num_interrupts",periph.irqcount);
vpm("clk_i","clk_sys_i");
vpm("rst_n_i","rst_n_i");
......@@ -3582,12 +3639,12 @@ vpm("reg_isr_i","eic_isr_clear_int");
vpm("reg_isr_wr_stb_i","eic_isr_write_int");
vpm("wb_irq_o","wb_int_o");
};
local a;
for o,t in ipairs(s)do
local o;
for a,t in ipairs(a)do
table_join(e,{vgm(string.format("g_irq%02x_mode",t.index),t.trigger)});
a=o;
o=a;
end
for t=a,31 do
for t=o,31 do
table_join(e,{vgm(string.format("g_irq%02x_mode",t),0)});
end
local t={vinstance("eic_irq_controller_inst","wbgen2_eic",e);};
......@@ -3763,35 +3820,34 @@ local s={
["hdl_prefix"]=e.hdl_prefix.."_CSR";
["no_std_regbank"]=true;
};
function gen_fifo_csr_field(d,n,t,a,h,o,r,i)
print("GenCSR Field "..t);
function gen_fifo_csr_field(a,i,t,r,h,o,d,n)
if(e.flags_bus==nil)then
return;
end
if inset(d,e.flags_bus)then
if inset(a,e.flags_bus)then
local t={
["__type"]=TYPE_FIELD;
["name"]=t;
["description"]=a;
["description"]=r;
["access_bus"]=READ_ONLY;
["access_dev"]=WRITE_ONLY;
["type"]=o;
["size"]=h;
["offset"]=r;
["c_prefix"]=n;
["hdl_prefix"]=n;
["offset"]=d;
["c_prefix"]=i;
["hdl_prefix"]=i;
["signals"]={};
["read_code"]={};
["ack_len"]=2;
};
local a=e.full_prefix.."_"..n.."_int";
if(i==nil)then
i=true
local a=e.full_prefix.."_"..i.."_int";
if(n==nil)then
n=true
else
i=false
n=false
end
if(i)then
table_join(e.maps,{vpm(e.nrdwr.."_"..n.."_o",a)});
if(n)then
table_join(e.maps,{vpm(e.nrdwr.."_"..i.."_o",a)});
end
table_join(t.signals,{signal(csel(o==MONOSTABLE,BIT,o),h,a)});
if(o==BIT)then
......@@ -3806,8 +3862,8 @@ t.write_code={vif(vequal(vi("rddata_reg",t.offset),1),{va(a,1)})};
t.ackgen_code={va(a,0)}
end
table.insert(s,t);
elseif(i)then
table_join(e.maps,{vpm(e.nrdwr.."_"..n.."_o",vopenpin())});
elseif(n)then
table_join(e.maps,{vpm(e.nrdwr.."_"..i.."_o",vopenpin())});
end
end
gen_fifo_csr_field(FIFO_FULL,
......@@ -3973,8 +4029,8 @@ foreach_reg(ALL_REG_TYPES,function(e)
gen_abstract_code(e);
end);
local n={};
local i={};
local o={};
local i={};
foreach_field(function(e,t)
table_join(n,e.reset_code_main);
end);
......@@ -3983,27 +4039,27 @@ table_join(n,e.reset_code_main);
end);
foreach_reg({TYPE_REG},function(e)
foreach_subfield(e,function(e,t)
table_join(i,e.ackgen_code);
table_join(o,e.ackgen_code_pre);
table_join(o,e.ackgen_code);
table_join(i,e.ackgen_code_pre);
end);
table_join(i,e.ackgen_code);
table_join(o,e.ackgen_code_pre);
table_join(o,e.ackgen_code);
table_join(i,e.ackgen_code_pre);
end);
local e={};
foreach_reg({TYPE_REG},function(t)
local i=find_max(t,"acklen");
local o={};
local a={};
foreach_subfield(t,function(e,t)table_join(a,e.write_code);end);
foreach_subfield(t,function(e,t)table_join(o,e.read_code);end);
local o={};
foreach_subfield(t,function(e,t)table_join(o,e.write_code);end);
foreach_subfield(t,function(e,t)table_join(a,e.read_code);end);
local n=fill_unused_bits("rddata_reg",t);
table_join(a,t.write_code);
table_join(o,t.read_code);
table_join(o,t.write_code);
table_join(a,t.read_code);
local a={
vif(vequal("wb_we_i",1),{
a,
});
o,
});
a,
n
};
if(not(t.dont_emit_ack_code==true))then
......@@ -4071,7 +4127,7 @@ vcomment("advance the ACK generator shift register");
va(vi("ack_sreg",MAX_ACK_LENGTH-2,0),vi("ack_sreg",MAX_ACK_LENGTH-1,1));
va(vi("ack_sreg",MAX_ACK_LENGTH-1),0);
vif(vequal("ack_in_progress",1),{
vif(vequal(vi("ack_sreg",0),1),{i;va("ack_in_progress",0);},o);
vif(vequal(vi("ack_sreg",0),1),{o;va("ack_in_progress",0);},i);
},{
e
});
......@@ -4111,16 +4167,24 @@ table_join(e,{vcomment("Read & write lines decoder for RAMs");vcombprocess(a,t);
else
table_join(e,{vcomment("Drive the data output bus");va("wb_dat_o","rddata_reg")});
end
foreach_reg(ALL_REG_TYPES,function(t)
foreach_reg(ALL_REG_TYPES,
function(t)
ex_code={}
if(t.extra_code~=nil)then
table_join(e,{vcomment("extra code for reg/fifo/mem: "..t.name);});
table_join(e,t.extra_code);
table_join(ex_code,{vcomment("extra code for reg/fifo/mem: "..t.name);});
table_join(ex_code,t.extra_code);
end
foreach_subfield(t,function(t,a)
if(t.extra_code~=nil)then
table_join(e,{vcomment(t.name);t.extra_code});
foreach_subfield(t,
function(e,t)
if(e.extra_code~=nil)then
table_join(ex_code,{vcomment(e.name);e.extra_code});
end
end);
if(t.optional==nil)then
table_join(e,ex_code)
else
table_join(e,{vgenerate_if(vnot(vequal(t.optional,0)),ex_code)});
end
end);
if(address_bus_width>0)then
table_join(e,{va("rwaddr_reg","wb_adr_i");});
......@@ -4171,7 +4235,7 @@ function usage_complete()
print(e)
print(t)
end
function parse_args(a)
function parse_args(o)
local t={
help="h",
version="v",
......@@ -4186,8 +4250,8 @@ cstyle="s",
hstyle="H"
}
local e
local o
e,o=alt_getopt.get_opts(a,"hvC:D:K:l:V:s:f:H:p:",t)
local a
e,a=alt_getopt.get_opts(o,"hvC:D:K:l:V:s:f:H:p:",t)
for t,e in pairs(e)do
if t=="h"then
usage_complete()
......@@ -4224,11 +4288,11 @@ end
options.hdl_reg_style=e
end
end
if(a[o]==nil)then
if(o[a]==nil)then
usage()
os.exit(0)
end
input_wb_file=a[o];
input_wb_file=o[a];
end
parse_args(arg);
dofile(input_wb_file);
......
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