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Wishbone slave generator
Commit 93e0e4f4 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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fixed readback value of write-only (monostable) bits to 0. See Wesley's message… 

fixed readback value of write-only (monostable) bits to 0. See Wesley's message on white-rabbit-dev, dated 12/02/2013 for explanation
parent 50e10c5b
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Showing with 6 additions and 11 deletions
wbgen2
View file @ 93e0e4f4
......@@ -2506,7 +2506,7 @@ va(e.."_o",vand(e.."_int",vnot(e.."_dly0")));
});
t.reset_code_main={va(e.."_int",0)};
t.write_code={va(e.."_int",vi("wrdata_reg",t.offset))};
t.read_code={va(vi("rddata_reg",t.offset),vundefined())};
t.read_code={va(vi("rddata_reg",t.offset),0)};
t.ackgen_code={va(e.."_int",0)};
else
t.signals={signal(BIT,0,e.."_int"),
......@@ -2534,10 +2534,9 @@ va(e.."_o",vand(e.."_sync2",vnot(e.."_sync1")));
});};
t.reset_code_main={va(e.."_int",0);
va(e.."_int_delay",0);};
t.write_code={
va(e.."_int",vi("wrdata_reg",t.offset));
t.write_code={va(e.."_int",vi("wrdata_reg",t.offset));
va(e.."_int_delay",vi("wrdata_reg",t.offset));};
t.read_code={va(vi("rddata_reg",t.offset),vundefined())};
t.read_code={va(vi("rddata_reg",t.offset),0)};
t.ackgen_code_pre={va(e.."_int",e.."_int_delay");
va(e.."_int_delay",0);};
end
......@@ -2553,7 +2552,6 @@ t.acklen=1;
t.write_code={
va(e.."_int",vi("wrdata_reg",t.offset))};
t.read_code={va(vi("rddata_reg",t.offset),e.."_int")};
print("RV: ",t.reset_value)
t.reset_code_main={va(e.."_int",csel(t.reset_value==nil,0,t.reset_value))};
t.extra_code={va(e.."_o",e.."_int")};
elseif(t.access==ACC_RO_WO)then
......
wbgen_regbank.lua
View file @ 93e0e4f4
......@@ -61,8 +61,7 @@ function gen_hdl_code_monostable(field, reg)
field.reset_code_main = { va(prefix.."_int", 0) };
field.write_code = { va(prefix.."_int", vi("wrdata_reg", field.offset))};
-- va(vi("rddata_reg", field.offset), vundefined()) };
field.read_code = { va(vi("rddata_reg", field.offset), vundefined()) };
field.read_code = { va(vi("rddata_reg", field.offset), 0) };
field.ackgen_code = { va(prefix.."_int", 0) };
else
......@@ -100,11 +99,10 @@ function gen_hdl_code_monostable(field, reg)
va(prefix.."_int_delay", 0); };
field.write_code = { --va(vi("rddata_reg", field.offset), vundefined()),
va(prefix.."_int", vi("wrdata_reg", field.offset));
field.write_code = { va(prefix.."_int", vi("wrdata_reg", field.offset));
va(prefix.."_int_delay", vi("wrdata_reg", field.offset)); };
field.read_code = { va(vi("rddata_reg", field.offset), vundefined())};
field.read_code = { va(vi("rddata_reg", field.offset), 0)};
field.ackgen_code_pre = { va(prefix.."_int", prefix.."_int_delay");
va(prefix.."_int_delay", 0); };
......@@ -129,7 +127,6 @@ function gen_hdl_code_bit(field, reg)
field.write_code = { --va(vi("rddata_reg", field.offset), vundefined()),
va(prefix.."_int", vi("wrdata_reg", field.offset)) };
field.read_code = { va(vi("rddata_reg", field.offset), prefix.."_int") };
print("RV: ", field.reset_value)
field.reset_code_main = { va(prefix.."_int", csel(field.reset_value == nil, 0, field.reset_value)) };
field.extra_code = { va(prefix.."_o", prefix.."_int") };
......
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