Maintenance scheduled 24th July -- expect downtime along that day

Commit a281a99c authored by twlostow's avatar twlostow

HDL library: now uses general-cores (genrams) to instantiate RAM/FIFO primitives

git-svn-id: http://svn.ohwr.org/wishbone-gen@23 4537843c-45c2-4d80-8546-c3283569414f
parent 72a0f7f0
files = ["wbgen2_dpssram.vhd",
"wbgen2_eic.vhd",
"wbgen2_fifo_async.vhd",
"wbgen2_fifo_sync.vhd",
"wbgen2_pkg.vhd"]
modules = {"git" : "git@ohwr.org:hdl-core-lib/general-cores.git" }
This diff is collapsed.
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
library wbgen2;
entity wbgen2_fifo_async is
generic (
g_size : integer;
g_width : integer;
g_usedw_size : integer
);
port
(
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
wr_clk_i : in std_logic;
wr_req_i : in std_logic;
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0)
);
end wbgen2_fifo_async;
architecture rtl of wbgen2_fifo_async is
component dcfifo
generic (
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
rdsync_delaypipe : natural;
underflow_checking : string;
use_eab : string;
wrsync_delaypipe : natural
);
port (
rdfull : out std_logic;
wrclk : in std_logic;
rdempty : out std_logic;
rdreq : in std_logic;
wrusedw : out std_logic_vector (g_usedw_size-1 downto 0);
wrfull : out std_logic;
wrempty : out std_logic;
rdclk : in std_logic;
q : out std_logic_vector (g_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector (g_width-1 downto 0);
rdusedw : out std_logic_vector (g_usedw_size-1 downto 0)
);
end component;
begin
dcfifo_component : dcfifo
generic map (
-- intended_device_family => "Cyclone III",
lpm_numwords => g_size,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => g_width,
lpm_widthu => g_usedw_size,
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
wrsync_delaypipe => 5
)
port map (
wrclk => wr_clk_i,
rdreq => rd_req_i,
rdclk => rd_clk_i,
wrreq => wr_req_i,
data => wr_data_i,
rdfull => rd_full_o,
rdempty => rd_empty_o,
wrusedw => wr_usedw_o,
wrfull => wr_full_o,
wrempty => wr_empty_o,
q => rd_data_o,
rdusedw => rd_usedw_o
);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
--use work.genram_pkg.all;
--use work.common_components.all;
--library wbgen2;
use work.wbgen2_pkg.all;
entity wbgen2_dpssram is
generic (
g_data_width : natural := 32;
g_size : natural := 1024;
g_addr_width : natural := 10;
g_dual_clock : boolean := true;
g_use_bwsel : boolean := true);
port (
clk_a_i : in std_logic;
clk_b_i : in std_logic;
addr_a_i : in std_logic_vector(g_addr_width-1 downto 0);
addr_b_i : in std_logic_vector(g_addr_width-1 downto 0);
data_a_i : in std_logic_vector(g_data_width-1 downto 0);
data_b_i : in std_logic_vector(g_data_width-1 downto 0);
data_a_o : out std_logic_vector(g_data_width-1 downto 0);
data_b_o : out std_logic_vector(g_data_width-1 downto 0);
bwsel_a_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
bwsel_b_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
rd_a_i : in std_logic;
rd_b_i : in std_logic;
wr_a_i : in std_logic;
wr_b_i : in std_logic
);
end wbgen2_dpssram;
architecture syn of wbgen2_dpssram is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function f_log2_size;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
begin
wrapped_dpram: generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_use_bwsel,
g_dual_clock => g_dual_clock)
port map (
rst_n_i => '1',
clka_i => clk_a_i,
bwea_i => bwsel_a_i,
wea_i => wr_a_i,
aa_i => addr_a_i,
da_i => data_a_i,
qa_o => data_a_o,
clkb_i => clk_b_i,
bweb_i => bwsel_b_i,
web_i => wr_b_i,
ab_i => addr_b_i,
db_i => data_b_i,
qb_o => data_b_o);
end syn;
......@@ -3,8 +3,7 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library wbgen2;
use wbgen2.all;
use work.wbgen2_pkg.all;
entity wbgen2_eic is
......
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wbgen2_pkg.all;
entity wbgen2_fifo_async is
generic (
g_size : integer;
g_width : integer;
g_usedw_size : integer
);
port
(
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
wr_clk_i : in std_logic;
wr_req_i : in std_logic;
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0)
);
end wbgen2_fifo_async;
architecture rtl of wbgen2_fifo_async is
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_rd_empty : boolean;
g_with_rd_full : boolean;
g_with_rd_almost_empty : boolean;
g_with_rd_almost_full : boolean;
g_with_rd_count : boolean;
g_with_wr_empty : boolean;
g_with_wr_full : boolean;
g_with_wr_almost_empty : boolean;
g_with_wr_almost_full : boolean;
g_with_wr_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
begin
wrapped_fifo: generic_async_fifo
generic map (
g_data_width => g_width,
g_size => g_size,
g_show_ahead => false,
g_with_rd_empty => true,
g_with_rd_full => true,
g_with_rd_almost_empty => false,
g_with_rd_almost_full => false,
g_with_rd_count => true,
g_with_wr_empty => true,
g_with_wr_full => true,
g_with_wr_almost_empty => false,
g_with_wr_almost_full => false,
g_with_wr_count => true,
g_almost_empty_threshold => 0,
g_almost_full_threshold => 0)
port map (
rst_n_i => '1',
clk_wr_i => wr_clk_i,
d_i => wr_data_i,
we_i => wr_req_i,
wr_empty_o => wr_empty_o,
wr_full_o => wr_full_o,
wr_almost_empty_o => open,
wr_almost_full_o => open,
wr_count_o => wr_usedw_o,
clk_rd_i => rd_clk_i,
q_o => rd_data_o,
rd_i => rd_req_i,
rd_empty_o => rd_empty_o,
rd_full_o => rd_full_o,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => rd_usedw_o);
end rtl;
......@@ -2,10 +2,8 @@
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
use work.wbgen2_pkg.all;
library wbgen2;
entity wbgen2_fifo_sync is
generic (
......@@ -13,7 +11,6 @@ entity wbgen2_fifo_sync is
g_size : integer;
g_usedw_size : integer);
port
(
clk_i : in std_logic;
......@@ -37,60 +34,72 @@ end wbgen2_fifo_sync;
architecture rtl of wbgen2_fifo_sync is
component scfifo
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function f_log2_size;
component generic_sync_fifo
generic (
add_ram_output_register : string;
-- intended_device_family : string;
lpm_numwords : natural;
lpm_showahead : string;
lpm_type : string;
lpm_width : natural;
lpm_widthu : natural;
overflow_checking : string;
underflow_checking : string;
use_eab : string
);
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean;
g_with_empty : boolean;
g_with_full : boolean;
g_with_almost_empty : boolean;
g_with_almost_full : boolean;
g_with_count : boolean;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
usedw : out std_logic_vector (g_usedw_size-1 downto 0);
rdreq : in std_logic;
empty : out std_logic;
clock : in std_logic;
q : out std_logic_vector (g_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector (g_width-1 downto 0);
full : out std_logic
);
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
signal empty_int, full_int : std_logic;
signal usedw_int : std_logic_vector(g_usedw_size -1 downto 0);
signal empty_int : std_logic;
signal full_int : std_logic;
signal usedw_int : std_logic_vector(g_usedw_size-1 downto 0);
begin
scfifo_component : scfifo
wrapped_fifo: generic_sync_fifo
generic map (
add_ram_output_register => "ON",
-- intended_device_family => "Cyclone III",
lpm_numwords => g_size,
lpm_showahead => "OFF",
lpm_type => "scfifo",
lpm_width => g_width,
lpm_widthu => g_usedw_size,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
g_data_width => g_width,
g_size => g_size,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true,
g_with_almost_empty => false,
g_with_almost_full => false,
g_with_count => true)
port map (
rdreq => rd_req_i,
clock => clk_i,
wrreq => wr_req_i,
data => wr_data_i,
usedw => usedw_int,
empty => empty_int,
q => rd_data_o,
full => full_int
);
rst_n_i => '1',
clk_i => clk_i,
d_i => wr_data_i,
we_i => wr_req_i,
q_o => rd_data_o,
rd_i => rd_req_i,
empty_o => empty_int,
full_o => full_int,
almost_empty_o => open,
almost_full_o => open,
count_o => usedw_int);
rd_empty_o <= empty_int;
rd_full_o <= full_int;
......
library ieee;
use ieee.std_logic_1164.all;
library wbgen2;
package wbgen2_pkg is
......
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