Maintenance scheduled 24th July -- expect downtime along that day

Commit bbeb98a0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

initial support for 'optional' parameter (conditional instantiation of RAMs and…

initial support for 'optional' parameter (conditional instantiation of RAMs and FIFOs depending on a user-defined generic value)
parent 490a61cc
#!/usr/bin/lua
-- -*- Mode: LUA; tab-width: 2 -*-
-- wbgen2, (c) 2010 Tomasz Wlostowski
-- CERN BE-Co-HT
-- wbgen2 - a simple Wishbone slave generator
-- (c) 2010-2013 CERN
-- CERN BE-CO-HT
-- LICENSED UNDER GPL v2
......@@ -107,6 +108,14 @@ function vif(cond, code, code_else)
return s;
end
function vgenerate_if(cond, code)
local s={};
s.t="generate_if";
s.cond={ cond };
s.code=code;
return s;
end
function vequal(a,b)
local s={};
s.t="eq";
......@@ -240,6 +249,7 @@ function port(type, nbits, dir, name, comment, extra_flags)
return t;
end
global_ports = {};
global_signals = {};
......@@ -292,9 +302,30 @@ function cgen_build_portlist()
return portlist;
end
function cgen_build_optional_list()
local t1={}
local t2={} -- fixme: extremely ugly
local j=1
for i,v in pairs(tree_2_table("optional")) do
if t1[v] == nil then
t1[v]=1
t2[j]=v
j=j+1
end
end
return t2
end
function cgen_find_sigport(name)
for i,v in pairs(g_portlist) do if(name == v.name) then return v; end end
for i,v in pairs(g_siglist) do if(name == v.name) then return v; end end
for i,v in pairs(g_optlist) do if(name == v) then
local gp = {}
gp.type = INTEGER;
gp.name = v;
return gp;
end end
die("cgen internal error: undefined signal '"..name.."'");
......@@ -304,6 +335,7 @@ end
function cgen_build_signals_ports()
g_portlist = cgen_build_portlist();
g_siglist = cgen_build_siglist();
g_optlist = cgen_build_optional_list();
end
cur_indent = 0;
......
......@@ -230,6 +230,27 @@ function cgen_vhdl_entity()
end
emit ("entity "..periph.hdl_entity.." is");
indent_right();
if(table.getn(g_optlist) ~= 0) then
emit ("generic (");
indent_right();
emiti()
for i,v in pairs(g_optlist) do
emiti();
emitx(v.." : integer := 1");
if(i ~= table.getn(g_optlist)) then
emit(";")
else
emit(");")
end
end
indent_left();
end
indent_left();
indent_right();
emit ("port (");
indent_right();
......@@ -245,7 +266,7 @@ function cgen_vhdl_entity()
emitx("-- "..port.comment.."\n");
end
print(port.name.." "..port.type)
-- print(port.name.." "..port.type)
-- generate code for the port
local line = string.format("%-40s : %-6s %s", port.name, port.dir, fieldtype_2_vhdl[port.type]);
......@@ -605,6 +626,25 @@ function cgen_generate_vhdl_code(tree)
end
end
-- function generates an if..else..end if control block.
function cgen_vhdl_generate_if(node)
if(g_gen_block_count == nil) then
g_gen_block_count = 0
else
g_gen_block_count = g_gen_block_count + 1
end
gname = string.format("genblock_%d", g_gen_block_count)
emiti(); emitx(gname..": if (");
-- recurse the condition block
recurse(node.cond);
emitx(") generate\n");
indent_right(); recurse(node.code); indent_left();
emit("end generate "..gname..";");
end
-- function generates a NOT unary expression.
function cgen_vhdl_not(node)
-- check type of node to be NOTed
......@@ -779,6 +819,7 @@ function cgen_generate_vhdl_code(tree)
["combprocess"] = cgen_vhdl_combprocess;
["assign"] = cgen_vhdl_assign;
["if"] = cgen_vhdl_if;
["generate_if"] = cgen_vhdl_generate_if;
["eq"] = cgen_vhdl_binary_op;
["add"] = cgen_vhdl_binary_op;
["sub"] = cgen_vhdl_binary_op;
......
......@@ -269,19 +269,33 @@ function gen_bus_logic_pipelined_wb(mode)
table_join(code, {vcomment("Drive the data output bus"); va("wb_dat_o", "rddata_reg") } );
end
foreach_reg(ALL_REG_TYPES, function(reg)
if(reg.extra_code ~= nil) then
table_join(code, {vcomment("extra code for reg/fifo/mem: "..reg.name);});
table_join(code, reg.extra_code);
end
foreach_reg(ALL_REG_TYPES,
function(reg)
ex_code = {}
if(reg.extra_code ~= nil) then
table_join(ex_code, {vcomment("extra code for reg/fifo/mem: "..reg.name);});
table_join(ex_code, reg.extra_code);
end
foreach_subfield(reg,
function(field, reg)
if (field.extra_code ~= nil) then
table_join(ex_code, {vcomment(field.name); field.extra_code});
end
end );
if(reg.optional == nil) then
table_join(code, ex_code)
else
table_join(code, {vgenerate_if(vnot(vequal(reg.optional, 0)), ex_code )} );
end
foreach_subfield(reg, function(field, reg)
if (field.extra_code ~= nil) then
table_join(code, {vcomment(field.name); field.extra_code});
end
end );
end);
if(address_bus_width > 0) then
table_join(code, { va("rwaddr_reg", "wb_adr_i"); });
......
......@@ -229,8 +229,6 @@ function fifo_wire_bus_ports(fifo)
function gen_fifo_csr_field(flag, field_prefix, field_name, field_desc, size, type, offset, do_map)
print("GenCSR Field "..field_name);
if(fifo.flags_bus == nil) then
return;
end
......
#!/usr/bin/lua
-- -*- Mode: LUA; tab-width: 2 -*-
-- wbgen2 - a simple Wishbone slave generator
-- (c) 2010 Tomasz Wlostowski
-- CERN BE-Co-HT
-- LICENSED UNDER GPL v2
function ram_wire_core_ports(ram)
local prefix = ram.full_prefix;
......@@ -112,7 +116,7 @@ function gen_code_ram(ram)
-- instantiate the RAM.
ram.extra_code = { vcomment ("RAM block instantiation for memory: "..ram.name);
vinstance (prefix.."_raminst", "wbgen2_dpssram", ram.maps );
vinstance (prefix.."_raminst", "wbgen2_dpssram", ram.maps );
};
ram.base = ram.select_bits * math.pow (2, address_bus_width - address_bus_select_bits);
......
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