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Wishbone slave generator
Commit c906a787 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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target_pipelined_wb: in case of an if-generate, also add a second… 

target_pipelined_wb: in case of an if-generate, also add a second (complementary) if-generate to drive all outputs when the if-generate condition is false
parent 8d431e7f
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Showing with 324 additions and 301 deletions
target_pipelined_wb.lua
View file @ c906a787
......@@ -290,7 +290,17 @@ function gen_bus_logic_pipelined_wb(mode)
if(reg.optional == nil) then
table_join(code, ex_code)
else
table_join(code, {vgenerate_if(vnot(vequal(reg.optional, 0)), ex_code )} );
table_join(code, {vgenerate_if(vnot(vequal(reg.optional, 0)), ex_code )} );
-- also create complementary if-generate to drive unused outputs when condition is false
gen_ex_code = {}
for i, v in ipairs(reg.ports) do
if v.dir == "out" then
table_join(gen_ex_code, {va(v.name, 0);});
end
end
if gen_ex_code ~= nil then
table_join(code, {vgenerate_if(vequal(reg.optional, 0), gen_ex_code )} );
end
end
end);
......
wbgen2
View file @ c906a787
#!/usr/bin/env lua
package.preload['alt_getopt']=(function(...)
local i,d,u,a,o=type,pairs,ipairs,io,os
local i,s,u,a,o=type,pairs,ipairs,io,os
module("alt_getopt")
local function c(t)
local e=1
local e=#t
local e={}
for a,t in t:gmatch("(%w)(:?)")do
e[a]=#t
local function r(e)
local t=1
local t=#e
local t={}
for e,a in e:gmatch("(%w)(:?)")do
t[e]=#a
end
return e
return t
end
local function r(t,e)
local function d(t,e)
a.stderr:write(t)
o.exit(e)
end
local function a(e)
r("Unknown option `-"..
d("Unknown option `-"..
(#e>1 and"-"or"")..e.."'\n",1)
end
local function l(t,e)
......@@ -31,13 +31,13 @@ end
end
return e
end
function get_ordered_opts(n,a,s)
function get_ordered_opts(n,o,a)
local t=1
local e=1
local i={}
local h={}
local o=c(a)
for t,e in d(s)do
local o=r(o)
for t,e in s(a)do
o[t]=e
end
while t<=#n do
......@@ -53,7 +53,7 @@ if s then
local t=a:sub(3,s-1)
t=l(o,t)
if o[t]==0 then
r("Bad usage of option `"..a.."'\n",1)
d("Bad usage of option `"..a.."'\n",1)
end
h[e]=a:sub(s+1)
i[e]=t
......@@ -64,7 +64,7 @@ if o[s]==0 then
i[e]=s
else
if t==#n then
r("Missed value for option `"..a.."'\n",1)
d("Missed value for option `"..a.."'\n",1)
end
h[e]=n[t+1]
i[e]=s
......@@ -74,14 +74,14 @@ end
e=e+1
elseif a:sub(1,1)=="-"then
local s
for d=2,a:len()do
local s=l(o,a:sub(d,d))
for r=2,a:len()do
local s=l(o,a:sub(r,r))
if o[s]==0 then
i[e]=s
e=e+1
elseif a:len()==d then
elseif a:len()==r then
if t==#n then
r("Missed value for option `-"..s.."'\n",1)
d("Missed value for option `-"..s.."'\n",1)
end
h[e]=n[t+1]
i[e]=s
......@@ -89,7 +89,7 @@ t=t+1
e=e+1
break
else
h[e]=a:sub(d+1)
h[e]=a:sub(r+1)
i[e]=s
e=e+1
break
......@@ -102,9 +102,9 @@ t=t+1
end
return i,t,h
end
function get_opts(t,o,a)
function get_opts(a,t,o)
local e={}
local t,i,o=get_ordered_opts(t,o,a)
local t,i,o=get_ordered_opts(a,t,o)
for a,t in u(t)do
if o[a]then
e[t]=o[a]
......@@ -176,22 +176,22 @@ die(t.." expected.");
end
return e;
end
function range2bits(e)
local t=e[1];
local a=e[2];
local e;
if(math.abs(t)>math.abs(a))then
e=math.abs(t);
function range2bits(t)
local e=t[1];
local a=t[2];
local t;
if(math.abs(e)>math.abs(a))then
t=math.abs(e);
else
e=math.abs(a);
t=math.abs(a);
end
local e=math.ceil(math.log(e)/math.log(2));
if(t<0)then
e=e+1;
local t=math.ceil(math.log(t)/math.log(2));
if(e<0)then
t=t+1;
end
return e;
return t;
end
function calc_size(e,t)
function calc_size(e,a)
if(e.type==MONOSTABLE or e.type==BIT)then
e.size=1;
elseif(e.type==SLV or e.type==PASS_THROUGH)then
......@@ -212,16 +212,16 @@ end
elseif(e.type==ENUM)then
die("ENUM-type fields are not yet supported. Sorry :(");
end
t.total_size=t.total_size+e.size;
a.total_size=a.total_size+e.size;
end
function foreach_reg(t,a,e)
function foreach_reg(a,t,e)
if(e==nil)then
e=periph;
end
for o,e in ipairs(e)do
if(type(e)=='table')then
if(e.__type~=nil and(match(e.__type,t)))then
a(e);
if(e.__type~=nil and(match(e.__type,a)))then
t(e);
end
end
end
......@@ -292,15 +292,15 @@ if(t==e)then return true;end
end
return false;
end
function inset(e,t)
for a,t in ipairs(t)do if(e==t)then return true;end end
function inset(t,e)
for a,e in ipairs(e)do if(t==e)then return true;end end
return false;
end
function csel(e,t,a)
function csel(e,a,t)
if(e)then
return t;
else
return a;
else
return t;
end
end
function check_field_types(e)
......@@ -324,13 +324,13 @@ return e;
end
return e;
end
function default_access(e,t,a,o)
function default_access(e,t,o,a)
if(e.type==t)then
if(e.access_bus==nil)then
e.access_bus=a;
e.access_bus=o;
end
if(e.access_dev==nil)then
e.access_dev=o;
e.access_dev=a;
end
end
end
......@@ -375,9 +375,9 @@ end
function log2up(e)
return math.ceil(math.log(e)/math.log(2));
end
function is_power_of_2(t)
for e=1,24 do
if(t==math.pow(2,e))then return true;end
function is_power_of_2(e)
for t=1,24 do
if(e==math.pow(2,t))then return true;end
end
return false;
end
......@@ -432,36 +432,36 @@ table.insert(t,e);
end
end
function tree_2_table(e)
local a={};
foreach_reg({TYPE_REG,TYPE_RAM,TYPE_FIFO,TYPE_IRQ},function(t)
if(t[e]~=nil)then
if(type(t[e])=='table')then
table_join(a,t[e]);
local t={};
foreach_reg({TYPE_REG,TYPE_RAM,TYPE_FIFO,TYPE_IRQ},function(a)
if(a[e]~=nil)then
if(type(a[e])=='table')then
table_join(t,a[e]);
else
table.insert(a,t[e]);
table.insert(t,a[e]);
end
end
foreach_subfield(t,function(t,o)
if(t[e]~=nil)then
if(type(t[e])=='table')then
table_join(a,t[e]);
foreach_subfield(a,function(a,o)
if(a[e]~=nil)then
if(type(a[e])=='table')then
table_join(t,a[e]);
else
table.insert(a,t[e]);
table.insert(t,a[e]);
end
end
end);
end);
return a;
return t;
end
function remove_duplicates(t)
function count_entries(a,t)
function remove_duplicates(o)
function count_entries(t,a)
local o,o,e;
e=0;
for o,a in ipairs(a)do if(a==t)then e=e+1;end end
for o,t in ipairs(t)do if(t==a)then e=e+1;end end
return e;
end
local e={};
for a,t in ipairs(t)do
for a,t in ipairs(o)do
local a=count_entries(e,t);
if(a==0)then
table.insert(e,t);
......@@ -470,38 +470,38 @@ end
return e;
end
function wbgen_count_subblocks()
local a=0;
local t=0;
local e=0;
local a=0;
local o=0;
local t=0;
foreach_reg({TYPE_RAM},function(e)a=a+1;end);
foreach_reg({TYPE_REG},function(e)o=o+1;end);
foreach_reg({TYPE_RAM},function(e)t=t+1;end);
foreach_reg({TYPE_REG},function(e)a=a+1;end);
foreach_reg({TYPE_FIFO},function(t)e=e+1;end);
foreach_reg({TYPE_IRQ},function(e)t=t+1;end);
periph.ramcount=a;
foreach_reg({TYPE_IRQ},function(e)o=o+1;end);
periph.ramcount=t;
periph.fifocount=e;
periph.regcount=o;
periph.irqcount=t;
if(a+e+o+t==0)then
periph.regcount=a;
periph.irqcount=o;
if(t+e+a+o==0)then
die("Can't generate an empty peripheral. Define some regs, RAMs, FIFOs or IRQs, please...");
end
end
function deepcopy(i)
local a={}
local function t(e)
local o={}
local function a(e)
if type(e)~="table"then
return e
elseif a[e]then
return a[e]
elseif o[e]then
return o[e]
end
local o={}
a[e]=o
for a,e in pairs(e)do
o[t(a)]=t(e)
local t={}
o[e]=t
for o,e in pairs(e)do
t[a(o)]=a(e)
end
return setmetatable(o,getmetatable(e))
return setmetatable(t,getmetatable(e))
end
return t(i)
return a(i)
end
function va(t,a)
local e={};
......@@ -510,12 +510,12 @@ e.dst=t;
e.src=a;
return e;
end
function vi(t,a,o)
function vi(a,o,t)
local e={};
e.t="index";
e.name=t;
e.h=a;
e.l=o;
e.name=a;
e.h=o;
e.l=t;
return e;
end
function vinstance(o,a,t)
......@@ -526,11 +526,11 @@ e.component=a;
e.maps=t;
return e;
end
function vpm(t,a)
function vpm(a,t)
local e={};
e.t="portmap";
e.to=t;
e.from=a;
e.to=a;
e.from=t;
return e;
end
function vgm(t,a)
......@@ -547,12 +547,12 @@ e.slist=t;
e.code=a;
return e;
end
function vsyncprocess(a,o,t)
function vsyncprocess(t,a,o)
local e={};
e.t="syncprocess";
e.clk=a;
e.rst=o;
e.code=t;
e.clk=t;
e.rst=a;
e.code=o;
return e;
end
function vreset(a,t)
......@@ -568,19 +568,19 @@ e.t="posedge";
e.code=t;
return e;
end
function vif(t,a,o)
function vif(a,t,o)
local e={};
e.t="if";
e.cond={t};
e.code=a;
e.cond={a};
e.code=t;
e.code_else=o;
return e;
end
function vgenerate_if(a,t)
function vgenerate_if(t,a)
local e={};
e.t="generate_if";
e.cond={a};
e.code=t;
e.cond={t};
e.code=a;
return e;
end
function vequal(t,a)
......@@ -597,11 +597,11 @@ e.a=a;
e.b=t;
return e;
end
function vor(t,a)
function vor(a,t)
local e={};
e.t="or";
e.a=t;
e.b=a;
e.a=a;
e.b=t;
return e;
end
function vnot(t)
......@@ -610,18 +610,18 @@ e.t="not";
e.a=t;
return e;
end
function vswitch(a,t)
function vswitch(t,a)
local e={};
e.t="switch";
e.a=a;
e.code=t;
e.a=t;
e.code=a;
return e;
end
function vcase(a,t)
function vcase(t,a)
local e={};
e.t="case";
e.a=a;
e.code=t;
e.a=t;
e.code=a;
return e;
end
function vcasedefault(t)
......@@ -636,11 +636,11 @@ e.t="comment";
e.str=t;
return e;
end
function vsub(a,t)
function vsub(t,a)
local e={};
e.t="sub";
e.a=a;
e.b=t;
e.a=t;
e.b=a;
return e;
end
function vothers(t)
......@@ -659,12 +659,12 @@ local e={}
e.t="undefined";
return e;
end
function signal(o,a,i,t)
function signal(o,a,t,i)
local e={}
e.comment=t;
e.comment=i;
e.type=o;
e.range=a;
e.name=i;
e.name=t;
return e;
end
VPORT_WB=1;
......@@ -729,12 +729,12 @@ end
function cgen_build_optional_list()
local o={}
local a={}
local e=1
for i,t in pairs(tree_2_table("optional"))do
if o[t]==nil then
o[t]=1
a[e]=t
e=e+1
local t=1
for i,e in pairs(tree_2_table("optional"))do
if o[e]==nil then
o[e]=1
a[t]=e
t=t+1
end
end
return a
......@@ -832,23 +832,23 @@ function gen_vhdl_bin_literal(i,a)
if(a==1)then
return string.format("'%d'",csel(i==0,0,1));
end
local e='\"';
local s,o,n,t;
local t='\"';
local s,o,n,e;
o=i;
t=math.pow(2,a-1);
e=math.pow(2,a-1);
if(i==nil)then
for t=1,a do
e=e.."X";
for e=1,a do
t=t.."X";
end
else
for a=1,a do
n=math.floor(o/t);
e=e..csel(n>0,"1","0");
o=o%t;
t=t/2;
n=math.floor(o/e);
t=t..csel(n>0,"1","0");
o=o%e;
e=e/2;
end
end
return e..'\"';
return t..'\"';
end
function strip_periph_prefix(e)
return string.gsub(e,"^"..periph.hdl_prefix.."\_","")
......@@ -921,17 +921,17 @@ emit("return tmp;");
emit("end function;");
emit("end package body;");
end
function cgen_vhdl_port_struct(o)
emit("type t_"..periph.hdl_prefix.."_"..o.."_registers is record");
function cgen_vhdl_port_struct(a)
emit("type t_"..periph.hdl_prefix.."_"..a.."_registers is record");
indent_right();
local a={};
local t={};
for e=1,table.getn(g_portlist)do
local e=g_portlist[e];
if(e.is_reg_port==true and e.dir==o)then
table.insert(a,e);
if(e.is_reg_port==true and e.dir==a)then
table.insert(t,e);
end
end
for t,e in ipairs(a)do
for t,e in ipairs(t)do
local t=csel(e.type==SLV and e.range==1,"std_logic",fieldtype_2_vhdl[e.type]);
local t=string.format("%-40s : %s",strip_periph_prefix(e.name),t);
if(e.range>1)then
......@@ -943,17 +943,17 @@ end
emit("end record;");
indent_left();
emit("");
emit("constant c_"..periph.hdl_prefix.."_"..o.."_registers_init_value: t_"..periph.hdl_prefix.."_"..o.."_registers := (");
emit("constant c_"..periph.hdl_prefix.."_"..a.."_registers_init_value: t_"..periph.hdl_prefix.."_"..a.."_registers := (");
indent_right();
for e=1,table.getn(a)do
local t=a[e];
line=strip_periph_prefix(t.name).." => ";
if(t.range>1)then
for a=1,table.getn(t)do
local e=t[a];
line=strip_periph_prefix(e.name).." => ";
if(e.range>1)then
line=line.."(others => '0')"
else
line=line.."'0'"
end
if(e~=table.getn(a))then
if(a~=table.getn(t))then
line=line..",";
end
emit(line);
......@@ -1217,16 +1217,16 @@ else
die("unsupported assignment: "..t.name.." "..e.name);end
else die("unsupported assignment: "..t.name.." "..e.name);end
end
function cgen_vhdl_assign(e)
local t=node_typesize(e.dst);
local e=node_typesize(e.src);
if(e.type==EXPRESSION)then
function cgen_vhdl_assign(t)
local e=node_typesize(t.dst);
local t=node_typesize(t.src);
if(t.type==EXPRESSION)then
emiti();
emitx(gen_subrange(t).." <= ");
recurse({e.code});
emitx(gen_subrange(e).." <= ");
recurse({t.code});
emitx(";\n");
else
emit(gen_subrange(t).." <= "..gen_vhdl_typecvt(t,e)..";");
emit(gen_subrange(e).." <= "..gen_vhdl_typecvt(e,t)..";");
end
end
function cgen_vhdl_if(e)
......@@ -1482,7 +1482,7 @@ function cgen_verilog_ending()
indent_left();
emit("endmodule");
end
function cgen_generate_verilog_code(i)
function cgen_generate_verilog_code(n)
local a=false;
function find_code(e,t)
for a,e in ipairs(e)do if((e.t~=nil)and(e.t==t))then return e;end end
......@@ -1687,29 +1687,29 @@ end
end
emit("endcase");
end
function cgen_verilog_instance(t)
function cgen_verilog_instance(a)
local o=0;
local a=0;
local i=0;
local e;
emitx(t.component.." ");
for t,e in pairs(t.maps)do
emitx(a.component.." ");
for t,e in pairs(a.maps)do
if(e.t=="genmap")then
a=a+1;
i=i+1;
elseif(e.t=="portmap")then
o=o+1;
end
end
if(a>0)then
if(i>0)then
indent_right();
emit("# (");
indent_right();
e=1;
for t,o in pairs(t.maps)do
if(o.t=="genmap")then
local t=o.from;
for t,a in pairs(a.maps)do
if(a.t=="genmap")then
local t=a.from;
if(t=="true")then t=1;
elseif(t=="false")then t=0;end
emit(string.format(".%-20s(%s)",o.to,t)..csel(e==a,"",","));
emit(string.format(".%-20s(%s)",a.to,t)..csel(e==i,"",","));
e=e+1;
end
end
......@@ -1719,10 +1719,10 @@ indent_left();
end
if(o>0)then
indent_right();
emit(t.name.." ( ");
emit(a.name.." ( ");
indent_right();
e=1;
for a,t in pairs(t.maps)do
for a,t in pairs(a.maps)do
if(t.t=="portmap")then
local a=node_typesize(t.from);
emit(string.format(".%-20s(%s)",t.to,gen_subrange(a))..csel(e==o,"",","));
......@@ -1738,23 +1738,23 @@ end
function cgen_verilog_openpin(e)
emitx("");
end
function cgen_verilog_combprocess(e)
local t=true;
function cgen_verilog_combprocess(t)
local e=true;
emiti();
emitx("always @(");
a=true;
for a,e in pairs(e.slist)do
if(t)then
t=false;
for a,t in pairs(t.slist)do
if(e)then
e=false;
else
emitx(" or ");
end
emitx(e);
emitx(t);
end
emit(")");
emit("begin");
indent_right();
recurse(e.code);
recurse(t.code);
indent_left();
a=false;
emit("end");
......@@ -1794,7 +1794,7 @@ cgen_new_snippet();
cgen_verilog_header();
local a=cgen_get_snippet();
cgen_new_snippet();
recurse(i);
recurse(n);
cgen_verilog_ending();
local e=cgen_get_snippet();
cgen_new_snippet();
......@@ -1863,7 +1863,11 @@ emit("");
emit("#ifndef __WBGEN2_REGDEFS_"..string.upper(string.gsub(input_wb_file,"%.","_")))
emit("#define __WBGEN2_REGDEFS_"..string.upper(string.gsub(input_wb_file,"%.","_")))
emit("");
emit("#include <inttypes.h>");
emit("#ifdef __KERNEL__")
emit("#include <linux/types.h>")
emit("#else")
emit("#include <inttypes.h>")
emit("#endif")
emit("");
emit("#if defined( __GNUC__)");
emit("#define PACKED __attribute__ ((packed))");
......@@ -1981,15 +1985,15 @@ end
function htable_trstyle(e,a,t)
tbl.data[e].style=t;
end
function htable_frame(a,t,e,o)
if(o==nil)then
a.data[t][e].extra='style="border: solid 1px black;"';
function htable_frame(o,a,e,t)
if(t==nil)then
o.data[a][e].extra='style="border: solid 1px black;"';
else
a.data[t][e].extra='style="border-left: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
a.data[t][o].extra='style="border-right: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
if(o>e+1)then
for e=e+1,o-1 do
a.data[t][e].extra='border-top: solid 1px black; border-bottom: solid 1px black;';
o.data[a][e].extra='style="border-left: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
o.data[a][t].extra='style="border-right: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
if(t>e+1)then
for e=e+1,t-1 do
o.data[a][e].extra='border-top: solid 1px black; border-bottom: solid 1px black;';
end
end
end
......@@ -2027,11 +2031,11 @@ emit("</tr>");
end
emit("</table>");
end
function has_any_ports(t)
local e=false;
if(t.ports~=nil)then return true;end
foreach_subfield(t,function(t)if(t.ports~=nil)then e=true;end end);
return e;
function has_any_ports(e)
local t=false;
if(e.ports~=nil)then return true;end
foreach_subfield(e,function(e)if(e.ports~=nil)then t=true;end end);
return t;
end
function htable_add_row(e,t)
if(t>e.rows)then
......@@ -2045,27 +2049,27 @@ end
e.rows=t;
end
end
function hlink(t,e)
return'<A href="'..t..'">'..e..'</a>';
function hlink(e,t)
return'<A href="'..e..'">'..t..'</a>';
end
function hitem(e)
return'<li>'..e..'</li>';
end
function hanchor(t,e)
return'<a name="'..t..'">'..e..'</a>';
function hanchor(e,t)
return'<a name="'..e..'">'..t..'</a>';
end
doc_toc={};
function hsection(a,t,o)
function hsection(t,a,o)
local e={};
local i=0;
e.id_mangled="sect_"..a.."_"..t;
e.key=a*1e3+t;
if(t~=0)then
e.id_mangled="sect_"..t.."_"..a;
e.key=t*1e3+a;
if(a~=0)then
e.level=2;
e.id=a.."."..t..".";
e.id=t.."."..a..".";
else
e.level=1;
e.id=a..".";
e.id=t..".";
end
e.name=o;
table.insert(doc_toc,e);
......@@ -2114,44 +2118,44 @@ end
end);
cgen_doc_symbol(t);
end
function cgen_doc_mem_symbol(t)
local e={};
for t,a in pairs(t.ports)do
local t=a;
function cgen_doc_mem_symbol(e)
local t={};
for e,a in pairs(e.ports)do
local e=a;
if(string.find(a.name,"_i")~=nil)then
t.is_wb=true;
e.is_wb=true;
else
t.is_wb=false;
e.is_wb=false;
end
table.insert(e,t);
table.insert(t,e);
end
if(t.clock~=nil)then
local t=port(BIT,0,"in",t.clock);
t.is_wb=true;
table.insert(e,t);
if(e.clock~=nil)then
local e=port(BIT,0,"in",e.clock);
e.is_wb=true;
table.insert(t,e);
end
cgen_doc_symbol(e);
cgen_doc_symbol(t);
end
function cgen_doc_symbol(o)
function cgen_doc_symbol(i)
local t=htable_new(3,5);
local a=1;
local e=1;
local i=true;
for o,e in pairs(o)do
local o=true;
for o,e in pairs(i)do
if(e.is_wb)then
htable_add_row(t,a);
cgen_doc_port(t.data[a],e,true);
a=a+1;
end
end
for o,a in ipairs(o)do
for i,a in ipairs(i)do
if(type(a)=="string")then
if(i==false)then
if(o==false)then
htable_add_row(t,e);
row=t.data[e];row[3].text="&nbsp;";
e=e+1;
else
i=false;
o=false;
end
htable_add_row(t,e);
local t=t.data[e];
......@@ -2225,19 +2229,19 @@ e[5].text=string.upper(t.c_prefix);
i=not i;
end
end);
foreach_reg({TYPE_RAM},function(t)
if(t.full_hdl_prefix~=nil)then
foreach_reg({TYPE_RAM},function(e)
if(e.full_hdl_prefix~=nil)then
htable_add_row(o,a);
local e=o.data[a];a=a+1;
e.style=csel(i,"tr_odd","tr_even");
e[1].style="td_code";
e[1].text=string.format("0x%x - 0x%x",t.base,t.base+math.pow(2,t.wrap_bits)*t.size-1);
e[2].text="MEM";
e[3].text=hlink("#"..string.upper(t.c_prefix),t.name);
e[4].style="td_code";
e[4].text=t.full_hdl_prefix;
e[5].style="td_code";
e[5].text=string.upper(t.c_prefix);
local t=o.data[a];a=a+1;
t.style=csel(i,"tr_odd","tr_even");
t[1].style="td_code";
t[1].text=string.format("0x%x - 0x%x",e.base,e.base+math.pow(2,e.wrap_bits)*e.size-1);
t[2].text="MEM";
t[3].text=hlink("#"..string.upper(e.c_prefix),e.name);
t[4].style="td_code";
t[4].text=e.full_hdl_prefix;
t[5].style="td_code";
t[5].text=string.upper(e.c_prefix);
i=not i;
end
end);
......@@ -2413,19 +2417,19 @@ cgen_new_snippet();
emit(hsection(3,0,"Register description"));
foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_reg(e);end end);
local o=cgen_get_snippet();
local a="";
local t="";
if(periph.ramcount>0)then
emit(hsection(4,0,"Memory blocks"));
cgen_new_snippet();
foreach_reg({TYPE_RAM},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_ram(e);end end);
a=cgen_get_snippet();
t=cgen_get_snippet();
end
local t="";
local a="";
if(periph.irqcount>0)then
cgen_new_snippet();
emit(hsection(5,0,"Interrupts"));
foreach_reg({TYPE_IRQ},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_irq(e);end end);
t=cgen_get_snippet();
a=cgen_get_snippet();
end
cgen_new_snippet();
cgen_doc_memmap();
......@@ -2435,8 +2439,8 @@ cgen_doc_header_and_toc();
emit(e);
emit(i);
emit(o);
emit(a);
emit(t);
emit(a);
emit('</BODY>');
emit('</HTML>');
cgen_write_current_snippet();
......@@ -2854,19 +2858,19 @@ cgen_new_snippet();
emit("\\subsubsection{Register description}");
foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_reg(e);end end);
local o=cgen_get_snippet();
local a="";
local t="";
if(periph.ramcount>0)then
emit("\\subsubsection{Memory blocks}");
cgen_new_snippet();
foreach_reg({TYPE_RAM},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_ram(e);end end);
a=cgen_get_snippet();
t=cgen_get_snippet();
end
local t="";
local a="";
if(periph.irqcount>0)then
cgen_new_snippet();
emit("\\subsubsection{Interrupts}");
foreach_reg({TYPE_IRQ},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_lx_irq(e);end end);
t=cgen_get_snippet();
a=cgen_get_snippet();
end
cgen_new_snippet();
cgen_doc_lx_memmap();
......@@ -2875,8 +2879,8 @@ cgen_new_snippet();
cgen_doc_lx_header_and_toc();
emit(e);
emit(o);
emit(a);
emit(t);
emit(a);
cgen_write_current_snippet();
end
function gen_hdl_field_prefix(a,e)
......@@ -3511,8 +3515,8 @@ end
function wbgen_generate_eic()
if(periph.irqcount==0)then return;end
local t=0;
local n={};
local s={["__type"]=TYPE_REG;
local s={};
local i={["__type"]=TYPE_REG;
["__blockindex"]=1e6;
["align"]=8;
["name"]="Interrupt disable register";
......@@ -3528,7 +3532,7 @@ signal(BIT,0,"eic_idr_write_int");};
["extra_code"]={va(vi("eic_idr_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true;
};
local i={["__type"]=TYPE_REG;
local a={["__type"]=TYPE_REG;
["__blockindex"]=1000001;
["align"]=1;
["name"]="Interrupt enable register";
......@@ -3563,7 +3567,7 @@ signal(BIT,0,"eic_isr_write_int");};
["extra_code"]={va(vi("eic_isr_clear_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true;
};
local a={["__type"]=TYPE_REG;
local n={["__type"]=TYPE_REG;
["__blockindex"]=1000003;
["align"]=1;
["name"]="Interrupt mask register";
......@@ -3578,9 +3582,9 @@ local a={["__type"]=TYPE_REG;
foreach_reg({TYPE_IRQ},function(e)
e.index=t;
t=t+1;
table.insert(n,{["index"]=e.index;["trigger"]=e.trigger;});
table.insert(s,{["index"]=e.index;["trigger"]=e.trigger;});
fix_prefix(e);
local t={
local s={
["__blockindex"]=e.index;
["__type"]=TYPE_FIELD;
["type"]=BIT;
......@@ -3591,7 +3595,7 @@ local t={
["access_bus"]=READ_WRITE;
["access_dev"]=READ_WRITE;
};
local n={
local t={
["__blockindex"]=e.index;
["__type"]=TYPE_FIELD;
["type"]=BIT;
......@@ -3602,7 +3606,7 @@ local n={
["access_bus"]=WRITE_ONLY;
["access_dev"]=READ_ONLY;
};
local r={
local h={
["__blockindex"]=e.index;
["__type"]=TYPE_FIELD;
["type"]=BIT;
......@@ -3613,7 +3617,7 @@ local r={
["access_bus"]=WRITE_ONLY;
["access_dev"]=READ_ONLY;
};
local h={
local r={
["__blockindex"]=e.index;
["__type"]=TYPE_FIELD;
["type"]=BIT;
......@@ -3633,17 +3637,17 @@ end
if(e.mask_line==true)then
table_join(e.ports,{port(BIT,0,"out",e.full_prefix.."_mask_o");});
end
table.insert(s,r);
table.insert(o,t);
table.insert(a,h);
table.insert(i,n);
table.insert(i,h);
table.insert(o,s);
table.insert(n,r);
table.insert(a,t);
end);
add_global_signals({
signal(SLV,periph.irqcount,"irq_inputs_vector_int");
});
table.insert(periph,s);
table.insert(periph,i);
table.insert(periph,a);
table.insert(periph,n);
table.insert(periph,o);
local e={vgm("g_num_interrupts",periph.irqcount);
vpm("clk_i","clk_sys_i");
......@@ -3660,12 +3664,12 @@ vpm("reg_isr_i","eic_isr_clear_int");
vpm("reg_isr_wr_stb_i","eic_isr_write_int");
vpm("wb_irq_o","wb_int_o");
};
local a;
for o,t in ipairs(n)do
table_join(e,{vgm(string.format("g_irq%02x_mode",t.index),t.trigger)});
a=o;
local t;
for o,a in ipairs(s)do
table_join(e,{vgm(string.format("g_irq%02x_mode",a.index),a.trigger)});
t=o;
end
for t=a,31 do
for t=t,31 do
table_join(e,{vgm(string.format("g_irq%02x_mode",t),0)});
end
local t={vinstance("eic_irq_controller_inst","wbgen2_eic",e);};
......@@ -3841,34 +3845,34 @@ local s={
["hdl_prefix"]=e.hdl_prefix.."_CSR";
["no_std_regbank"]=true;
};
function gen_fifo_csr_field(d,n,t,a,h,o,r,i)
function gen_fifo_csr_field(a,i,t,d,h,o,r,n)
if(e.flags_bus==nil)then
return;
end
if inset(d,e.flags_bus)then
if inset(a,e.flags_bus)then
local t={
["__type"]=TYPE_FIELD;
["name"]=t;
["description"]=a;
["description"]=d;
["access_bus"]=READ_ONLY;
["access_dev"]=WRITE_ONLY;
["type"]=o;
["size"]=h;
["offset"]=r;
["c_prefix"]=n;
["hdl_prefix"]=n;
["c_prefix"]=i;
["hdl_prefix"]=i;
["signals"]={};
["read_code"]={};
["ack_len"]=2;
};
local a=e.full_prefix.."_"..n.."_int";
if(i==nil)then
i=true
local a=e.full_prefix.."_"..i.."_int";
if(n==nil)then
n=true
else
i=false
n=false
end
if(i)then
table_join(e.maps,{vpm(e.nrdwr.."_"..n.."_o",a)});
if(n)then
table_join(e.maps,{vpm(e.nrdwr.."_"..i.."_o",a)});
end
table_join(t.signals,{signal(csel(o==MONOSTABLE,BIT,o),h,a)});
if(o==BIT)then
......@@ -3884,8 +3888,8 @@ table_join(t.read_code,{va(vi("rddata_reg",t.offset),0)});
t.ackgen_code={va(a,0)}
end
table.insert(s,t);
elseif(i)then
table_join(e.maps,{vpm(e.nrdwr.."_"..n.."_o",vopenpin())});
elseif(n)then
table_join(e.maps,{vpm(e.nrdwr.."_"..i.."_o",vopenpin())});
end
end
gen_fifo_csr_field(FIFO_FULL,
......@@ -4050,31 +4054,31 @@ gen_pipelined_wb_signals(e);
foreach_reg(ALL_REG_TYPES,function(e)
gen_abstract_code(e);
end);
local n={};
local i={};
local o={};
local n={};
foreach_field(function(e,t)
table_join(i,e.reset_code_main);
table_join(n,e.reset_code_main);
end);
foreach_reg(ALL_REG_TYPES,function(e)
table_join(i,e.reset_code_main);
table_join(n,e.reset_code_main);
end);
foreach_reg({TYPE_REG},function(e)
foreach_subfield(e,function(e,t)
table_join(o,e.ackgen_code);
table_join(n,e.ackgen_code_pre);
table_join(i,e.ackgen_code);
table_join(o,e.ackgen_code_pre);
end);
table_join(o,e.ackgen_code);
table_join(n,e.ackgen_code_pre);
table_join(i,e.ackgen_code);
table_join(o,e.ackgen_code_pre);
end);
local e={};
foreach_reg({TYPE_REG},function(t)
local i=find_max(t,"acklen");
local n=find_max(t,"acklen");
local o={};
local a={};
foreach_subfield(t,function(e,t)table_join(a,e.write_code);end);
foreach_subfield(t,function(e,t)table_join(o,e.read_code);end);
local n=fill_unused_bits("rddata_reg",t);
local i=fill_unused_bits("rddata_reg",t);
table_join(a,t.write_code);
table_join(o,t.read_code);
local a={
......@@ -4082,10 +4086,10 @@ vif(vequal("wb_we_i",1),{
a,
});
o,
n
i
};
if(not(t.dont_emit_ack_code==true))then
table_join(a,{va(vi("ack_sreg",math.max(i-1,0)),1);});
table_join(a,{va(vi("ack_sreg",math.max(n-1,0)),1);});
table_join(a,{va("ack_in_progress",1);});
end
if(regbank_address_bits>0)then
......@@ -4106,13 +4110,13 @@ local t={};
if(periph.fifocount+periph.regcount>0)then
t={vcase(0,e);};
end
foreach_reg({TYPE_RAM},function(e)
local a=csel(options.register_data_output,1,0);
table_join(t,{vcase(e.select_bits,{
foreach_reg({TYPE_RAM},function(a)
local e=csel(options.register_data_output,1,0);
table_join(t,{vcase(a.select_bits,{
vif(vequal("rd_int",1),{
va(vi("ack_sreg",0),1);
},{
va(vi("ack_sreg",a),1);
va(vi("ack_sreg",e),1);
});
va("ack_in_progress",1);
});});
......@@ -4142,14 +4146,14 @@ vreset(0,{
va("ack_sreg",0);
va("ack_in_progress",0);
va("rddata_reg",0);
i
n
});
vposedge({
vcomment("advance the ACK generator shift register");
va(vi("ack_sreg",MAX_ACK_LENGTH-2,0),vi("ack_sreg",MAX_ACK_LENGTH-1,1));
va(vi("ack_sreg",MAX_ACK_LENGTH-1),0);
vif(vequal("ack_in_progress",1),{
vif(vequal(vi("ack_sreg",0),1),{o;va("ack_in_progress",0);},n);
vif(vequal(vi("ack_sreg",0),1),{i;va("ack_in_progress",0);},o);
},{
e
});
......@@ -4158,20 +4162,20 @@ e
};
if(periph.ramcount>0)then
if(not options.register_data_output)then
local t={"rddata_reg","rwaddr_reg"};
local a={};
local o={vswitch(vi("rwaddr_reg",address_bus_width-1,address_bus_width-address_bus_select_bits),a);};
local o={vcomment("Data output multiplexer process");vcombprocess(t,o);};
local a={"rddata_reg","rwaddr_reg"};
local t={};
local o={vswitch(vi("rwaddr_reg",address_bus_width-1,address_bus_width-address_bus_select_bits),t);};
local o={vcomment("Data output multiplexer process");vcombprocess(a,o);};
foreach_reg({TYPE_RAM},function(e)
table.insert(t,e.full_prefix.."_rddata_int");
local t={va(vi("wb_dat_o",e.width-1,0),e.full_prefix.."_rddata_int");};
table.insert(a,e.full_prefix.."_rddata_int");
local a={va(vi("wb_dat_o",e.width-1,0),e.full_prefix.."_rddata_int");};
if(e.width<DATA_BUS_WIDTH)then
table_join(t,{va(vi("wb_dat_o",DATA_BUS_WIDTH-1,e.width),0);});
table_join(a,{va(vi("wb_dat_o",DATA_BUS_WIDTH-1,e.width),0);});
end
table_join(a,{vcase(e.select_bits,t);});
table_join(t,{vcase(e.select_bits,a);});
end);
table.insert(t,"wb_adr_i");
table_join(a,{vcasedefault(va("wb_dat_o","rddata_reg"));});
table.insert(a,"wb_adr_i");
table_join(t,{vcasedefault(va("wb_dat_o","rddata_reg"));});
table_join(e,o);
end
local a={"wb_adr_i","rd_int","wr_int"};
......@@ -4206,6 +4210,15 @@ if(t.optional==nil)then
table_join(e,ex_code)
else
table_join(e,{vgenerate_if(vnot(vequal(t.optional,0)),ex_code)});
gen_ex_code={}
for t,e in ipairs(t.ports)do
if e.dir=="out"then
table_join(gen_ex_code,{va(e.name,0);});
end
end
if gen_ex_code~=nil then
table_join(e,{vgenerate_if(vequal(t.optional,0),gen_ex_code)});
end
end
end);
if(address_bus_width>0)then
......@@ -4257,7 +4270,7 @@ function usage_complete()
print(e)
print(t)
end
function parse_args(o)
function parse_args(a)
local t={
help="h",
version="v",
......@@ -4272,8 +4285,8 @@ cstyle="s",
hstyle="H"
}
local e
local a
e,a=alt_getopt.get_opts(o,"hvC:D:K:l:V:s:f:H:p:",t)
local o
e,o=alt_getopt.get_opts(a,"hvC:D:K:l:V:s:f:H:p:",t)
for t,e in pairs(e)do
if t=="h"then
usage_complete()
......@@ -4310,11 +4323,11 @@ end
options.hdl_reg_style=e
end
end
if(o[a]==nil)then
if(a[o]==nil)then
usage()
os.exit(0)
end
input_wb_file=o[a];
input_wb_file=a[o];
end
parse_args(arg);
dofile(input_wb_file);
......
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