Commit cc5a5c00 authored by Dimitris Lampridis's avatar Dimitris Lampridis

vhdl: get rid of "internal signals for (foreseen) compatibility". They are not…

vhdl: get rid of "internal signals for (foreseen) compatibility". They are not used and generate a ton of warnings
parent 4f884cdc
...@@ -45,14 +45,8 @@ local width = math.max(1, address_bus_width); ...@@ -45,14 +45,8 @@ local width = math.max(1, address_bus_width);
local wb_sigs = { signal(SLV, MAX_ACK_LENGTH, "ack_sreg"), local wb_sigs = { signal(SLV, MAX_ACK_LENGTH, "ack_sreg"),
signal(SLV, DATA_BUS_WIDTH, "rddata_reg"), signal(SLV, DATA_BUS_WIDTH, "rddata_reg"),
signal(SLV, DATA_BUS_WIDTH, "wrdata_reg"), signal(SLV, DATA_BUS_WIDTH, "wrdata_reg"),
signal(SLV, DATA_BUS_WIDTH/8 , "bwsel_reg"),
signal(SLV, width, "rwaddr_reg"), signal(SLV, width, "rwaddr_reg"),
signal(BIT, 0, "ack_in_progress"), signal(BIT, 0, "ack_in_progress")
signal(BIT, 0, "wr_int"),
signal(BIT, 0, "rd_int"),
signal(SLV, DATA_BUS_WIDTH, "allones"),
signal(SLV, DATA_BUS_WIDTH, "allzeros")
}; };
add_global_signals(wb_sigs); add_global_signals(wb_sigs);
...@@ -179,15 +173,8 @@ function gen_bus_logic_pipelined_wb(mode) ...@@ -179,15 +173,8 @@ function gen_bus_logic_pipelined_wb(mode)
fsmcode = { vif(vand(vequal("wb_cyc_i", 1), vequal("wb_stb_i", 1)), { fsmcode } ); }; fsmcode = { vif(vand(vequal("wb_cyc_i", 1), vequal("wb_stb_i", 1)), { fsmcode } ); };
local code = { local code = {
vcomment("Some internal signals assignments. For (foreseen) compatibility with other bus standards."); vcomment("Some internal signals assignments");
va("wrdata_reg", "wb_dat_i"); va("wrdata_reg", "wb_dat_i");
va("bwsel_reg", "wb_sel_i");
va("rd_int", vand("wb_cyc_i", vand("wb_stb_i", vnot("wb_we_i"))));
va("wr_int", vand("wb_cyc_i", vand("wb_stb_i", "wb_we_i")));
va("allones", vothers(1));
va("allzeros", vothers(0));
vcomment(""); vcomment("");
vcomment("Main register bank access process."); vcomment("Main register bank access process.");
......
...@@ -39,15 +39,9 @@ local width = math.max(1, address_bus_width); ...@@ -39,15 +39,9 @@ local width = math.max(1, address_bus_width);
local wb_sigs = { signal(SLV, MAX_ACK_LENGTH, "ack_sreg"), local wb_sigs = { signal(SLV, MAX_ACK_LENGTH, "ack_sreg"),
signal(SLV, DATA_BUS_WIDTH, "rddata_reg"), signal(SLV, DATA_BUS_WIDTH, "rddata_reg"),
signal(SLV, DATA_BUS_WIDTH, "wrdata_reg"), signal(SLV, DATA_BUS_WIDTH, "wrdata_reg"),
signal(SLV, DATA_BUS_WIDTH/8 , "bwsel_reg"),
signal(SLV, width, "rwaddr_reg"), signal(SLV, width, "rwaddr_reg"),
signal(BIT, 0, "ack_in_progress"), signal(BIT, 0, "ack_in_progress"),
signal(BIT, 0, "wr_int"), signal(BIT, 0, "bus_clock_int")
signal(BIT, 0, "rd_int"),
signal(BIT, 0, "bus_clock_int"),
signal(SLV, DATA_BUS_WIDTH, "allones"),
signal(SLV, DATA_BUS_WIDTH, "allzeros")
}; };
add_global_signals(wb_sigs); add_global_signals(wb_sigs);
...@@ -174,16 +168,9 @@ function gen_bus_logic_wishbone() ...@@ -174,16 +168,9 @@ function gen_bus_logic_wishbone()
fsmcode = { vif(vand(vequal("wb_cyc_i", 1), vequal("wb_stb_i", 1)), { fsmcode } ); }; fsmcode = { vif(vand(vequal("wb_cyc_i", 1), vequal("wb_stb_i", 1)), { fsmcode } ); };
local code = { local code = {
vcomment("Some internal signals assignments. For (foreseen) compatibility with other bus standards."); vcomment("Some internal signals assignments");
va("wrdata_reg", "wb_data_i"); va("wrdata_reg", "wb_data_i");
va("bwsel_reg", "wb_sel_i");
va("bus_clock_int", "wb_clk_i"); va("bus_clock_int", "wb_clk_i");
va("rd_int", vand("wb_cyc_i", vand("wb_stb_i", vnot("wb_we_i"))));
va("wr_int", vand("wb_cyc_i", vand("wb_stb_i", "wb_we_i")));
va("allones", vothers(1));
va("allzeros", vothers(0));
vcomment(""); vcomment("");
vcomment("Main register bank access process."); vcomment("Main register bank access process.");
......
...@@ -4058,13 +4058,8 @@ local e=math.max(1,address_bus_width); ...@@ -4058,13 +4058,8 @@ local e=math.max(1,address_bus_width);
local e={signal(SLV,MAX_ACK_LENGTH,"ack_sreg"), local e={signal(SLV,MAX_ACK_LENGTH,"ack_sreg"),
signal(SLV,DATA_BUS_WIDTH,"rddata_reg"), signal(SLV,DATA_BUS_WIDTH,"rddata_reg"),
signal(SLV,DATA_BUS_WIDTH,"wrdata_reg"), signal(SLV,DATA_BUS_WIDTH,"wrdata_reg"),
signal(SLV,DATA_BUS_WIDTH/8,"bwsel_reg"),
signal(SLV,e,"rwaddr_reg"), signal(SLV,e,"rwaddr_reg"),
signal(BIT,0,"ack_in_progress"), signal(BIT,0,"ack_in_progress")
signal(BIT,0,"wr_int"),
signal(BIT,0,"rd_int"),
signal(SLV,DATA_BUS_WIDTH,"allones"),
signal(SLV,DATA_BUS_WIDTH,"allzeros")
}; };
add_global_signals(e); add_global_signals(e);
end end
...@@ -4153,13 +4148,8 @@ e={vswitch(vi("rwaddr_reg",address_bus_width-1,address_bus_width-address_bus_sel ...@@ -4153,13 +4148,8 @@ e={vswitch(vi("rwaddr_reg",address_bus_width-1,address_bus_width-address_bus_sel
end end
e={vif(vand(vequal("wb_cyc_i",1),vequal("wb_stb_i",1)),{e});}; e={vif(vand(vequal("wb_cyc_i",1),vequal("wb_stb_i",1)),{e});};
local e={ local e={
vcomment("Some internal signals assignments. For (foreseen) compatibility with other bus standards."); vcomment("Some internal signals assignments");
va("wrdata_reg","wb_dat_i"); va("wrdata_reg","wb_dat_i");
va("bwsel_reg","wb_sel_i");
va("rd_int",vand("wb_cyc_i",vand("wb_stb_i",vnot("wb_we_i"))));
va("wr_int",vand("wb_cyc_i",vand("wb_stb_i","wb_we_i")));
va("allones",vothers(1));
va("allzeros",vothers(0));
vcomment(""); vcomment("");
vcomment("Main register bank access process."); vcomment("Main register bank access process.");
vsyncprocess("clk_sys_i","rst_n_i",{ vsyncprocess("clk_sys_i","rst_n_i",{
......
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