fixed 'load' signal bug in SLV-type RW/RW registers

git-svn-id: http://svn.ohwr.org/wishbone-gen@19 4537843c-45c2-4d80-8546-c3283569414f

fixed 'load' signal bug in SLV-type RW/RW registers
git-svn-id: http://svn.ohwr.org/wishbone-gen@19 4537843c-45c2-4d80-8546-c3283569414f
d20fa15c · twlostow · 54091524 · d20fa15c
Commit d20fa15c authored Jul 05, 2010 by twlostow
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wbgen_regbank.lua wbgen_regbank.lua +1 -1

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--- a/wbgen_regbank.lua
+++ b/wbgen_regbank.lua
@@ -361,7 +361,7 @@ function gen_hdl_code_slv(field, reg)
 		    field.acklen = 					1;
 		    
 		    field.read_code = 			{ va(vir("rddata_reg", field), prefix.."_i"); };
-		    field.write_code = 			{ va(prefix.."_load_o", 0); };
+		    field.write_code = 			{ va(prefix.."_load_o", 1); };
 		    field.extra_code =			{ va(prefix.."_o", vir("wrdata_reg", field)); };
 		    field.ackgen_code_pre = { va(prefix.."_load_o", 0);};
 		    field.ackgen_code = 		{ va(prefix.."_load_o", 0); };