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Wishbone slave generator
Commit e0ce14ba authored by Benoit Rat's avatar Benoit Rat
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wbgen2: update squished binary (v0.7.0-epics)

parent df03935a
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Showing with 533 additions and 412 deletions
wbgen2
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#!/usr/bin/env lua
package.preload['alt_getopt']=(function(...)
local i,r,u,a,o=type,pairs,ipairs,io,os
local n,r,u,a,o=type,pairs,ipairs,io,os
module("alt_getopt")
local function c(t)
local function i(t)
local e=1
local e=#t
local e={}
......@@ -23,7 +23,7 @@ local function l(t,e)
if not t[e]then
a(e)
end
while i(t[e])=="string"do
while n(t[e])=="string"do
e=t[e]
if not t[e]then
a(e)
......@@ -31,14 +31,14 @@ end
end
return e
end
function get_ordered_opts(n,a,h)
function get_ordered_opts(n,a,s)
local t=1
local e=1
local i={}
local s={}
local o=c(a)
for t,e in r(h)do
o[t]=e
local o={}
local h={}
local i=i(a)
for t,e in r(s)do
i[t]=e
end
while t<=#n do
local a=n[t]
......@@ -48,49 +48,49 @@ break
elseif a=="-"then
break
elseif a:sub(1,2)=="--"then
local h=a:find("=",1,true)
if h then
local t=a:sub(3,h-1)
t=l(o,t)
if o[t]==0 then
local s=a:find("=",1,true)
if s then
local t=a:sub(3,s-1)
t=l(i,t)
if i[t]==0 then
d("Bad usage of option `"..a.."'\n",1)
end
s[e]=a:sub(h+1)
i[e]=t
h[e]=a:sub(s+1)
o[e]=t
else
local h=a:sub(3)
h=l(o,h)
if o[h]==0 then
i[e]=h
local s=a:sub(3)
s=l(i,s)
if i[s]==0 then
o[e]=s
else
if t==#n then
d("Missed value for option `"..a.."'\n",1)
end
s[e]=n[t+1]
i[e]=h
h[e]=n[t+1]
o[e]=s
t=t+1
end
end
e=e+1
elseif a:sub(1,1)=="-"then
local h
local s
for r=2,a:len()do
local h=l(o,a:sub(r,r))
if o[h]==0 then
i[e]=h
local s=l(i,a:sub(r,r))
if i[s]==0 then
o[e]=s
e=e+1
elseif a:len()==r then
if t==#n then
d("Missed value for option `-"..h.."'\n",1)
d("Missed value for option `-"..s.."'\n",1)
end
s[e]=n[t+1]
i[e]=h
h[e]=n[t+1]
o[e]=s
t=t+1
e=e+1
break
else
s[e]=a:sub(r+1)
i[e]=h
h[e]=a:sub(r+1)
o[e]=s
e=e+1
break
end
......@@ -100,7 +100,7 @@ break
end
t=t+1
end
return i,t,s
return o,t,h
end
function get_opts(t,o,a)
local e={}
......@@ -214,14 +214,14 @@ die("ENUM-type fields are not yet supported. Sorry :(");
end
t.total_size=t.total_size+e.size;
end
function foreach_reg(t,a,e)
function foreach_reg(a,t,e)
if(e==nil)then
e=periph;
end
for o,e in ipairs(e)do
if(type(e)=='table')then
if(e.__type~=nil and(match(e.__type,t)))then
a(e);
if(e.__type~=nil and(match(e.__type,a)))then
t(e);
end
end
end
......@@ -254,27 +254,27 @@ end
print("Align ",e.name,e.align,o,a);
return a;
end
function calc_field_offset(t,e)
local a=e.current_offset;
if(e.__type==TYPE_FIFO)then
local o=align(t,a);
if((o%DATA_BUS_WIDTH)+t.size>DATA_BUS_WIDTH)then
t.align=DATA_BUS_WIDTH;
a=align(t,a);
function calc_field_offset(e,t)
local a=t.current_offset;
if(t.__type==TYPE_FIFO)then
local o=align(e,a);
if((o%DATA_BUS_WIDTH)+e.size>DATA_BUS_WIDTH)then
e.align=DATA_BUS_WIDTH;
a=align(e,a);
else
a=o;
end
e.current_offset=a+t.size;
t.offset=a;
t.current_offset=a+e.size;
e.offset=a;
else
a=align(t,a);
e.current_offset=a+t.size;
t.offset=a;
a=align(e,a);
t.current_offset=a+e.size;
e.offset=a;
end
t.offset_unaligned=e.current_offset_unaligned;
e.current_offset_unaligned=e.current_offset_unaligned+t.size;
if(e.__type==TYPE_REG and e.current_offset>DATA_BUS_WIDTH)then
die("Total size of register '"..e.name.."' ("..e.current_offset..") exceeds data bus width ("..DATA_BUS_WIDTH..")");
e.offset_unaligned=t.current_offset_unaligned;
t.current_offset_unaligned=t.current_offset_unaligned+e.size;
if(t.__type==TYPE_REG and t.current_offset>DATA_BUS_WIDTH)then
die("Total size of register '"..t.name.."' ("..t.current_offset..") exceeds data bus width ("..DATA_BUS_WIDTH..")");
end
end
function calc_num_fields(t,e)
......@@ -285,22 +285,22 @@ function die(e)
print("Error: "..e);
os.exit(-1);
end
function match(e,t)
function match(t,e)
local a,a;
for a,t in pairs(t)do
if(e==t)then return true;end
for a,e in pairs(e)do
if(t==e)then return true;end
end
return false;
end
function inset(e,t)
for a,t in ipairs(t)do if(e==t)then return true;end end
function inset(t,e)
for a,e in ipairs(e)do if(t==e)then return true;end end
return false;
end
function csel(e,a,t)
if(e)then
return a;
else
function csel(a,t,e)
if(a)then
return t;
else
return e;
end
end
function check_field_types(e)
......@@ -324,10 +324,10 @@ return e;
end
return e;
end
function default_access(e,a,o,t)
if(e.type==a)then
function default_access(e,o,a,t)
if(e.type==o)then
if(e.access_bus==nil)then
e.access_bus=o;
e.access_bus=a;
end
if(e.access_dev==nil)then
e.access_dev=t;
......@@ -375,9 +375,9 @@ end
function log2up(e)
return math.ceil(math.log(e)/math.log(2));
end
function is_power_of_2(t)
for e=1,24 do
if(t==math.pow(2,e))then return true;end
function is_power_of_2(e)
for t=1,24 do
if(e==math.pow(2,t))then return true;end
end
return false;
end
......@@ -454,10 +454,10 @@ end);
return a;
end
function remove_duplicates(t)
function count_entries(a,t)
function count_entries(t,a)
local o,o,e;
e=0;
for o,a in ipairs(a)do if(a==t)then e=e+1;end end
for o,t in ipairs(t)do if(t==a)then e=e+1;end end
return e;
end
local e={};
......@@ -470,19 +470,19 @@ end
return e;
end
function wbgen_count_subblocks()
local o=0;
local a=0;
local t=0;
local e=0;
local o=0;
foreach_reg({TYPE_RAM},function(e)a=a+1;end);
foreach_reg({TYPE_REG},function(t)e=e+1;end);
foreach_reg({TYPE_FIFO},function(e)t=t+1;end);
foreach_reg({TYPE_IRQ},function(e)o=o+1;end);
periph.ramcount=a;
periph.fifocount=t;
periph.regcount=e;
periph.irqcount=o;
if(a+t+e+o==0)then
foreach_reg({TYPE_RAM},function(e)o=o+1;end);
foreach_reg({TYPE_REG},function(e)t=t+1;end);
foreach_reg({TYPE_FIFO},function(e)a=a+1;end);
foreach_reg({TYPE_IRQ},function(t)e=e+1;end);
periph.ramcount=o;
periph.fifocount=a;
periph.regcount=t;
periph.irqcount=e;
if(o+a+t+e==0)then
die("Can't generate an empty peripheral. Define some regs, RAMs, FIFOs or IRQs, please...");
end
end
......@@ -503,34 +503,34 @@ return setmetatable(a,getmetatable(e))
end
return t(i)
end
function va(a,t)
function va(t,a)
local e={};
e.t="assign";
e.dst=a;
e.src=t;
e.dst=t;
e.src=a;
return e;
end
function vi(o,t,a)
function vi(t,a,o)
local e={};
e.t="index";
e.name=o;
e.h=t;
e.l=a;
e.name=t;
e.h=a;
e.l=o;
return e;
end
function vinstance(a,o,t)
function vinstance(t,o,a)
local e={};
e.t="instance";
e.name=a;
e.name=t;
e.component=o;
e.maps=t;
e.maps=a;
return e;
end
function vpm(t,a)
function vpm(a,t)
local e={};
e.t="portmap";
e.to=t;
e.from=a;
e.to=a;
e.from=t;
return e;
end
function vgm(a,t)
......@@ -568,19 +568,19 @@ e.t="posedge";
e.code=t;
return e;
end
function vif(o,t,a)
function vif(t,a,o)
local e={};
e.t="if";
e.cond={o};
e.code=t;
e.code_else=a;
e.cond={t};
e.code=a;
e.code_else=o;
return e;
end
function vgenerate_if(t,a)
function vgenerate_if(a,t)
local e={};
e.t="generate_if";
e.cond={t};
e.code=a;
e.cond={a};
e.code=t;
return e;
end
function vequal(t,a)
......@@ -636,11 +636,11 @@ e.t="comment";
e.str=t;
return e;
end
function vsub(a,t)
function vsub(t,a)
local e={};
e.t="sub";
e.a=a;
e.b=t;
e.a=t;
e.b=a;
return e;
end
function vothers(t)
......@@ -659,23 +659,23 @@ local e={}
e.t="undefined";
return e;
end
function signal(o,a,t,i)
function signal(o,i,a,t)
local e={}
e.comment=i;
e.comment=t;
e.type=o;
e.range=a;
e.name=t;
e.range=i;
e.name=a;
return e;
end
VPORT_WB=1;
VPORT_REG=2;
function port(a,o,n,i,s,t)
function port(a,o,s,i,n,t)
local e={}
e.comment=s;
e.comment=n;
e.type=a;
e.range=o;
e.name=i;
e.dir=n;
e.dir=s;
if(t~=nil)then
if(t==VPORT_WB)then
e.is_wb=true;
......@@ -727,17 +727,17 @@ table_join(e,tree_2_table("ports"));
return e;
end
function cgen_build_optional_list()
local a={}
local o={}
local t=1
for i,e in pairs(tree_2_table("optional"))do
if a[e]==nil then
a[e]=1
o[t]=e
t=t+1
local a={}
local e=1
for i,t in pairs(tree_2_table("optional"))do
if o[t]==nil then
o[t]=1
a[e]=t
e=e+1
end
end
return o
return a
end
function cgen_find_sigport(e)
for a,t in pairs(g_portlist)do if(e==t.name)then return t;end end
......@@ -922,17 +922,17 @@ emit("return tmp;");
emit("end function;");
emit("end package body;");
end
function cgen_vhdl_port_struct(a)
emit("type t_"..periph.hdl_prefix.."_"..a.."_registers is record");
function cgen_vhdl_port_struct(o)
emit("type t_"..periph.hdl_prefix.."_"..o.."_registers is record");
indent_right();
local t={};
local a={};
for e=1,table.getn(g_portlist)do
local e=g_portlist[e];
if(e.is_reg_port==true and e.dir==a)then
table.insert(t,e);
if(e.is_reg_port==true and e.dir==o)then
table.insert(a,e);
end
end
for t,e in ipairs(t)do
for t,e in ipairs(a)do
local t=csel(e.type==SLV and e.range==1,"std_logic",fieldtype_2_vhdl[e.type]);
local t=string.format("%-40s : %s",strip_periph_prefix(e.name),t);
if(e.range>1)then
......@@ -944,17 +944,17 @@ end
emit("end record;");
indent_left();
emit("");
emit("constant c_"..periph.hdl_prefix.."_"..a.."_registers_init_value: t_"..periph.hdl_prefix.."_"..a.."_registers := (");
emit("constant c_"..periph.hdl_prefix.."_"..o.."_registers_init_value: t_"..periph.hdl_prefix.."_"..o.."_registers := (");
indent_right();
for e=1,table.getn(t)do
local a=t[e];
line=strip_periph_prefix(a.name).." => ";
if(a.range>1)then
for t=1,table.getn(a)do
local e=a[t];
line=strip_periph_prefix(e.name).." => ";
if(e.range>1)then
line=line.."(others => '0')"
else
line=line.."'0'"
end
if(e~=table.getn(t))then
if(t~=table.getn(a))then
line=line..",";
end
emit(line);
......@@ -1258,16 +1258,16 @@ else
die("unsupported assignment: "..t.name.." "..e.name);end
else die("unsupported assignment: "..t.name.." "..e.name);end
end
function cgen_vhdl_assign(t)
local e=node_typesize(t.dst);
local t=node_typesize(t.src);
if(t.type==EXPRESSION)then
function cgen_vhdl_assign(e)
local t=node_typesize(e.dst);
local e=node_typesize(e.src);
if(e.type==EXPRESSION)then
emiti();
emitx(gen_subrange(e).." <= ");
recurse({t.code});
emitx(gen_subrange(t).." <= ");
recurse({e.code});
emitx(";\n");
else
emit(gen_subrange(e).." <= "..gen_vhdl_typecvt(e,t)..";");
emit(gen_subrange(t).." <= "..gen_vhdl_typecvt(t,e)..";");
end
end
function cgen_vhdl_if(e)
......@@ -1356,25 +1356,25 @@ end
emit("end case;");
end
function cgen_vhdl_instance(t)
local o=0;
local a=0;
local o=0;
local e;
emit(t.name.." : "..t.component);
for t,e in pairs(t.maps)do
if(e.t=="genmap")then
a=a+1;
elseif(e.t=="portmap")then
o=o+1;
elseif(e.t=="portmap")then
a=a+1;
end
end
if(a>0)then
if(o>0)then
indent_right();
emit("generic map (");
indent_right();
e=1;
for o,t in pairs(t.maps)do
for a,t in pairs(t.maps)do
if(t.t=="genmap")then
emit(string.format("%-20s => %s",t.to,t.from)..csel(e==a,"",","));
emit(string.format("%-20s => %s",t.to,t.from)..csel(e==o,"",","));
e=e+1;
end
end
......@@ -1382,15 +1382,15 @@ indent_left();
emit(")");
indent_left();
end
if(o>0)then
if(a>0)then
indent_right();
emit("port map (");
indent_right();
e=1;
for a,t in pairs(t.maps)do
for o,t in pairs(t.maps)do
if(t.t=="portmap")then
local a=node_typesize(t.from);
emit(string.format("%-20s => %s",t.to,gen_subrange(a))..csel(e==o,"",","));
local o=node_typesize(t.from);
emit(string.format("%-20s => %s",t.to,gen_subrange(o))..csel(e==a,"",","));
e=e+1;
end
end
......@@ -1523,7 +1523,7 @@ function cgen_verilog_ending()
indent_left();
emit("endmodule");
end
function cgen_generate_verilog_code(i)
function cgen_generate_verilog_code(n)
local a=false;
function find_code(e,t)
for a,e in ipairs(e)do if((e.t~=nil)and(e.t==t))then return e;end end
......@@ -1670,33 +1670,33 @@ indent_left();
emit("end");
end
end
function cgen_verilog_not(e)
local t=node_typesize(e.a);
function cgen_verilog_not(t)
local e=node_typesize(t.a);
emitx("! ");
if(t.type==EXPRESSION)then
emitx("(");recurse({e.a});emitx(")");
if(e.type==EXPRESSION)then
emitx("(");recurse({t.a});emitx(")");
else
emitx(gen_subrange(t));
emitx(gen_subrange(e));
end
end
function cgen_verilog_binary_op(e)
local o=node_typesize(e.a);
local a=node_typesize(e.b);
local a=node_typesize(e.a);
local o=node_typesize(e.b);
local t=e.t;
if(o.type==EXPRESSION)then
if(a.type==EXPRESSION)then
emitx("(");recurse({e.a});emitx(")");
else
emitx(gen_subrange(o));
emitx(gen_subrange(a));
end
if(t=="eq")then emitx(" == ");end
if(t=="and")then emitx(" && ");end
if(t=="or")then emitx(" || ");end
if(t=="sub")then emitx(" - ");end
if(t=="add")then emitx(" + ");end
if(a.type==EXPRESSION)then
if(o.type==EXPRESSION)then
emitx("(");recurse({e.b});emitx(")");
else
emitx(gen_subrange(a));
emitx(gen_subrange(o));
end
end
function cgen_verilog_comment(e)
......@@ -1728,29 +1728,29 @@ end
end
emit("endcase");
end
function cgen_verilog_instance(t)
function cgen_verilog_instance(a)
local o=0;
local a=0;
local i=0;
local e;
emitx(t.component.." ");
for t,e in pairs(t.maps)do
emitx(a.component.." ");
for t,e in pairs(a.maps)do
if(e.t=="genmap")then
a=a+1;
i=i+1;
elseif(e.t=="portmap")then
o=o+1;
end
end
if(a>0)then
if(i>0)then
indent_right();
emit("# (");
indent_right();
e=1;
for t,o in pairs(t.maps)do
if(o.t=="genmap")then
local t=o.from;
for t,a in pairs(a.maps)do
if(a.t=="genmap")then
local t=a.from;
if(t=="true")then t=1;
elseif(t=="false")then t=0;end
emit(string.format(".%-20s(%s)",o.to,t)..csel(e==a,"",","));
emit(string.format(".%-20s(%s)",a.to,t)..csel(e==i,"",","));
e=e+1;
end
end
......@@ -1760,10 +1760,10 @@ indent_left();
end
if(o>0)then
indent_right();
emit(t.name.." ( ");
emit(a.name.." ( ");
indent_right();
e=1;
for a,t in pairs(t.maps)do
for a,t in pairs(a.maps)do
if(t.t=="portmap")then
local a=node_typesize(t.from);
emit(string.format(".%-20s(%s)",t.to,gen_subrange(a))..csel(e==o,"",","));
......@@ -1833,17 +1833,17 @@ end
end
cgen_new_snippet();
cgen_verilog_header();
local a=cgen_get_snippet();
local e=cgen_get_snippet();
cgen_new_snippet();
recurse(i);
recurse(n);
cgen_verilog_ending();
local e=cgen_get_snippet();
local a=cgen_get_snippet();
cgen_new_snippet();
cgen_verilog_module();
local t=cgen_get_snippet();
cgen_write_snippet(a);
cgen_write_snippet(t);
cgen_write_snippet(e);
cgen_write_snippet(t);
cgen_write_snippet(a);
end
function cgen_c_field_define(e,a,o)
local t;
......@@ -2022,6 +2022,118 @@ emit(string.format("%-45s %s","#define "..string.upper(periph.c_prefix).."_PERIP
emit("\n#endif");
cgen_write_current_snippet();
end
function cgen_db_field_records(e,t,a)
local a;
if(e.c_prefix==nil)then
return;
else
if(t.c_prefix==e.c_prefix or(e.c_prefix=="value"and t.num_fields==1))then
prefix_c=t.c_prefix;
else
prefix_c=t.c_prefix.."_"..e.c_prefix;
end
prefix_records=prefix_c:gsub("_(%a)",string.upper):gsub("^%l",string.upper);
end
emit("##---------------- '"..e.name.."' in '"..t.name.."'");
if(e.access_bus==WRITE_ONLY or e.access_bus==READ_WRITE)then
emit("");
if(e.type==BIT or e.type==MONOSTABLE)then
emit(string.format("record(bo, \"$(user):%s%s\")",prefix_records,"Cmd"));
emit("{");
emit(string.format("\tfield(%-5s,\"%s\")","DTYP","asynInt32"));
emit(string.format("\tfield(%-5s,\"%s%s\")","OUT","@asyn($(PORT),$(ADDR),$(TIMEOUT))",prefix_c));
else
emit(string.format("record(ao, \"$(user):%s%s\")",prefix_records,"Set"));
emit("{");
if(e.nbfp~=nil and e.nbfp>0)then
emit(string.format("\tfield(%-5s,\"%s\")","DTYP","asynFloat64"));
emit(string.format("\tfield(%-5s,\"%s\")","PREC","3"));
else
emit(string.format("\tfield(%-5s,\"%s\")","DTYP","asynInt32"));
end
emit(string.format("\tfield(%-5s,\"%s%s\")","OUT","@asyn($(PORT),$(ADDR),$(TIMEOUT))",prefix_c));
end
emit(string.format("\tfield(%-5s,\"%s\")","DESC",e.name));
emit("}");
end
if(e.access_bus==READ_ONLY or e.access_bus==READ_WRITE)then
emit("");
if(e.type==BIT or e.type==MONOSTABLE)then
emit(string.format("record(bi, \"$(user):%s%s\")",prefix_records,"Stat"));
emit("{");
emit(string.format("\tfield(%-5s,\"%s\")","DTYP","asynInt32"));
emit(string.format("\tfield(%-5s,\"%s%s\")","INP","@asyn($(PORT),$(ADDR),$(TIMEOUT))",prefix_c));
emit(string.format("\tfield(%-5s,\"%s\")","SCAN","I/O Intr"));
else
emit(string.format("record(ai, \"$(user):%s%s\")",prefix_records,"Rdbk"));
emit("{");
if(e.nbfp~=nil and e.nbfp>0)then
emit(string.format("\tfield(%-5s,\"%s\")","DTYP","asynFloat64"));
emit(string.format("\tfield(%-5s,\"%s\")","PREC","3"));
else
emit(string.format("\tfield(%-5s,\"%s\")","DTYP","asynInt32"));
end
emit(string.format("\tfield(%-5s,\"%s%s\")","INP","@asyn($(PORT),$(ADDR),$(TIMEOUT))",prefix_c));
emit(string.format("\tfield(%-5s,\"%s\")","SCAN","I/O Intr"));
end
emit(string.format("\tfield(%-5s,\"%s\")","DESC",e.name));
emit("}");
end
emit("");
end
function cgen_db_fields()
local t;
foreach_reg({TYPE_REG},function(e)
dbg("DOCREG: ",e.name,e.num_fields);
if(e.num_fields~=nil and e.num_fields>0)then
emit("##================ "..e.name.." ");
emit("");
t=0;
foreach_subfield(e,function(e,a)cgen_db_field_records(e,a,t);t=t+1;end);
emit("");
end
end);
foreach_reg({TYPE_RAM},function(e)
cgen_db_ramdefs(e);
end);
end
function cgen_db_fileheader()
emit("################################################################################");
emit("# ");
emit("# * File : "..options.output_epics_db_file);
emit("# * Author : auto-generated by wbgen2 from "..input_wb_file);
emit("# * Generated : "..os.date());
emit("# ");
emit("# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE "..input_wb_file);
emit("# ");
emit("#");
emit("# The $(user) is a MACRO that need to be defined in the st.cmd script");
emit("# This file hes been generated to be used with the AsynWBPortDriver class ");
emit("#");
emit("# Then the list of prefix are:");
emit("# ");
emit("# The list of sufix are: ");
emit("# Cmd (command), Rdbk (readback), Set (Setting), Stat (Status)");
emit("#");
emit("################################################################################");
emit("");
emit("");
emit("## Records definitions for slave peripheral: "..periph.name);
emit("## =============================================================================");
emit("");
emit("");
end
function cgen_generate_epics_db_code()
cgen_new_snippet();
cgen_db_fileheader();
cgen_db_fields();
emit("");
emit("## End of auto-generated: "..input_wb_file);
emit("## =============================================================================");
emit("");
emit("# User can fill its own records here");
cgen_write_current_snippet();
end
html_stylesheet='\
<!--\
BODY { background: white; color: black;\
......@@ -2058,21 +2170,21 @@ end
end
return e;
end
function htable_tdstyle(t,e,a)
tbl.data[t][e].style=a;
function htable_tdstyle(e,t,a)
tbl.data[e][t].style=a;
end
function htable_trstyle(t,a,e)
tbl.data[t].style=e;
function htable_trstyle(e,a,t)
tbl.data[e].style=t;
end
function htable_frame(e,o,a,t)
if(t==nil)then
e.data[o][a].extra='style="border: solid 1px black;"';
function htable_frame(o,a,t,e)
if(e==nil)then
o.data[a][t].extra='style="border: solid 1px black;"';
else
e.data[o][a].extra='style="border-left: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
e.data[o][t].extra='style="border-right: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
if(t>a+1)then
for t=a+1,t-1 do
e.data[o][t].extra='border-top: solid 1px black; border-bottom: solid 1px black;';
o.data[a][t].extra='style="border-left: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
o.data[a][e].extra='style="border-right: solid 1px black; border-top: solid 1px black; border-bottom: solid 1px black;';
if(e>t+1)then
for e=t+1,e-1 do
o.data[a][e].extra='border-top: solid 1px black; border-bottom: solid 1px black;';
end
end
end
......@@ -2110,11 +2222,11 @@ emit("</tr>");
end
emit("</table>");
end
function has_any_ports(t)
local e=false;
if(t.ports~=nil)then return true;end
foreach_subfield(t,function(t)if(t.ports~=nil)then e=true;end end);
return e;
function has_any_ports(e)
local t=false;
if(e.ports~=nil)then return true;end
foreach_subfield(e,function(e)if(e.ports~=nil)then t=true;end end);
return t;
end
function htable_add_row(e,a)
if(a>e.rows)then
......@@ -2138,17 +2250,17 @@ function hanchor(t,e)
return'<a name="'..t..'">'..e..'</a>';
end
doc_toc={};
function hsection(a,t,o)
function hsection(t,a,o)
local e={};
local i=0;
e.id_mangled="sect_"..a.."_"..t;
e.key=a*1e3+t;
if(t~=0)then
e.id_mangled="sect_"..t.."_"..a;
e.key=t*1e3+a;
if(a~=0)then
e.level=2;
e.id=a.."."..t..".";
e.id=t.."."..a..".";
else
e.level=1;
e.id=a..".";
e.id=t..".";
end
e.name=o;
table.insert(doc_toc,e);
......@@ -2198,43 +2310,43 @@ end);
cgen_doc_symbol(t);
end
function cgen_doc_mem_symbol(t)
local a={};
for e,t in pairs(t.ports)do
local e=t;
if(string.find(t.name,"_i")~=nil)then
e.is_wb=true;
local e={};
for t,a in pairs(t.ports)do
local t=a;
if(string.find(a.name,"_i")~=nil)then
t.is_wb=true;
else
e.is_wb=false;
t.is_wb=false;
end
table.insert(a,e);
table.insert(e,t);
end
if(t.clock~=nil)then
local e=port(BIT,0,"in",t.clock);
e.is_wb=true;
table.insert(a,e);
local t=port(BIT,0,"in",t.clock);
t.is_wb=true;
table.insert(e,t);
end
cgen_doc_symbol(a);
cgen_doc_symbol(e);
end
function cgen_doc_symbol(o)
function cgen_doc_symbol(i)
local t=htable_new(3,5);
local a=1;
local e=1;
local i=true;
for o,e in pairs(o)do
local o=true;
for o,e in pairs(i)do
if(e.is_wb)then
htable_add_row(t,a);
cgen_doc_port(t.data[a],e,true);
a=a+1;
end
end
for o,a in ipairs(o)do
for i,a in ipairs(i)do
if(type(a)=="string")then
if(i==false)then
if(o==false)then
htable_add_row(t,e);
row=t.data[e];row[3].text="&nbsp;";
e=e+1;
else
i=false;
o=false;
end
htable_add_row(t,e);
local t=t.data[e];
......@@ -2326,27 +2438,27 @@ end
end);
htable_emit(o);
end
function find_field_by_offset(e,t)
local a=nil;
foreach_subfield(e,function(e)if(t>=e.offset and t<=(e.offset+e.size-1))then a=e;end end);
return a;
function find_field_by_offset(e,a)
local t=nil;
foreach_subfield(e,function(e)if(a>=e.offset and a<=(e.offset+e.size-1))then t=e;end end);
return t;
end
function cgen_doc_fieldtable(h,i)
local e=70;
local t;
local e=1;
t=htable_new(2,8);
for e=1,8 do
t.data[1][e].style="td_bit";
t.data[1][e].text=string.format("%d",i+8-e);
local e;
local t=1;
e=htable_new(2,8);
for t=1,8 do
e.data[1][t].style="td_bit";
e.data[1][t].text=string.format("%d",i+8-t);
end
local a=i+7;
while(a>=i)do
local o=find_field_by_offset(h,a);
if(o==nil)then
t.data[2][e].style="td_unused";
t.data[2][e].text="-";
e=e+1;
e.data[2][t].style="td_unused";
e.data[2][t].text="-";
t=t+1;
a=a-1;
else
local n;
......@@ -2357,18 +2469,18 @@ n=o.offset;
end
local s=(a-n)+1;
dbg("ncells: ",s,"bit: ",a,"name: ",o.prefix);
t.data[2][e].colspan=s;
e.data[2][t].colspan=s;
local i;
i=o.c_prefix;
if(i==nil)then i=h.c_prefix;end
t.data[2][e].style="td_field";
t.data[2][e].text=csel(o.size>1,string.format("%s[%d:%d]",string.upper(i),a-o.offset,n-o.offset),string.upper(i));
htable_frame(t,2,e);
e.data[2][t].style="td_field";
e.data[2][t].text=csel(o.size>1,string.format("%s[%d:%d]",string.upper(i),a-o.offset,n-o.offset),string.upper(i));
htable_frame(e,2,t);
a=a-s;
e=e+1;
t=t+1;
end
end
htable_emit(t);
htable_emit(e);
end
function cgen_doc_access(e)
if(e==READ_ONLY)then
......@@ -2468,47 +2580,47 @@ emit("<p>"..string.gsub(t.description,"\n","<br>").."</p>");
end
end
cur_irq_no=1;
function cgen_doc_irq(t)
emit(hanchor(string.upper(t.c_prefix),""));
emit(hsection(5,cur_irq_no,t.name));
function cgen_doc_irq(e)
emit(hanchor(string.upper(e.c_prefix),""));
emit(hsection(5,cur_irq_no,e.name));
cur_irq_no=cur_irq_no+1;
local e=htable_new(3,2);
e.data[1][1].text="<b>HW prefix: </b>";
e.data[2][1].text="<b>C prefix: </b>";
e.data[3][1].text="<b>Trigger: </b>";
e.data[1][2].text=string.lower(periph.hdl_prefix.."_"..t.hdl_prefix);
e.data[2][2].text=string.upper(t.c_prefix);
local t=htable_new(3,2);
t.data[1][1].text="<b>HW prefix: </b>";
t.data[2][1].text="<b>C prefix: </b>";
t.data[3][1].text="<b>Trigger: </b>";
t.data[1][2].text=string.lower(periph.hdl_prefix.."_"..e.hdl_prefix);
t.data[2][2].text=string.upper(e.c_prefix);
local a={
[EDGE_RISING]="rising edge";
[EDGE_FALLING]="falling edge";
[LEVEL_0]="low level";
[LEVEL_1]="high level";
};
e.data[3][2].text=a[t.trigger];
htable_emit(e);
if(t.description~=nil)then
emit("<p>"..string.gsub(t.description,"\n","<br>").."</p>");
t.data[3][2].text=a[e.trigger];
htable_emit(t);
if(e.description~=nil)then
emit("<p>"..string.gsub(e.description,"\n","<br>").."</p>");
end
end
function cgen_generate_html_documentation()
cgen_new_snippet();cgen_doc_hdl_symbol();local i=cgen_get_snippet();
cgen_new_snippet();cgen_doc_hdl_symbol();local o=cgen_get_snippet();
cgen_new_snippet();
emit(hsection(3,0,"Register description"));
foreach_reg({TYPE_REG},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_reg(e);end end);
local o=cgen_get_snippet();
local a="";
local i=cgen_get_snippet();
local t="";
if(periph.ramcount>0)then
emit(hsection(4,0,"Memory blocks"));
cgen_new_snippet();
foreach_reg({TYPE_RAM},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_ram(e);end end);
a=cgen_get_snippet();
t=cgen_get_snippet();
end
local t="";
local a="";
if(periph.irqcount>0)then
cgen_new_snippet();
emit(hsection(5,0,"Interrupts"));
foreach_reg({TYPE_IRQ},function(e)if(e.no_docu==nil or e.no_docu==false)then cgen_doc_irq(e);end end);
t=cgen_get_snippet();
a=cgen_get_snippet();
end
cgen_new_snippet();
cgen_doc_memmap();
......@@ -2516,10 +2628,10 @@ local e=cgen_get_snippet();
cgen_new_snippet();
cgen_doc_header_and_toc();
emit(e);
emit(i);
emit(o);
emit(a);
emit(i);
emit(t);
emit(a);
emit('</BODY>');
emit('</HTML>');
cgen_write_current_snippet();
......@@ -3035,163 +3147,163 @@ t.ackgen_code_pre={va(e.."_int",e.."_int_delay");
va(e.."_int_delay",0);};
end
end
function gen_hdl_code_bit(t,a)
local e=gen_hdl_field_prefix(t,a);
t.prefix=e;
if(t.clock==nil)then
if(t.access==ACC_RW_RO)then
t.ports={port(BIT,0,"out",e.."_o","Port for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={signal(BIT,0,e.."_int")};
t.acklen=1;
t.write_code={
va(e.."_int",vi("wrdata_reg",t.offset))};
t.read_code={va(vi("rddata_reg",t.offset),e.."_int")};
t.reset_code_main={va(e.."_int",csel(t.reset_value==nil,0,t.reset_value))};
t.extra_code={va(e.."_o",e.."_int")};
elseif(t.access==ACC_RO_WO)then
t.ports={port(BIT,0,"in",e.."_i","Port for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={};
t.acklen=1;
t.write_code={};
t.read_code={va(vi("rddata_reg",t.offset),e.."_i")};
t.reset_code_main={};
t.extra_code={};
elseif(t.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..t.name..")");
elseif(t.access==ACC_RW_RW)then
if(t.load==LOAD_EXT)then
t.ports={port(BIT,0,"out",e.."_o","Ports for BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG),
port(BIT,0,"in",e.."_i",nil,VPORT_REG),
port(BIT,0,"out",e.."_load_o",nil,VPORT_REG)};
t.acklen=1;
t.read_code={va(vi("rddata_reg",t.offset),e.."_i")};
t.write_code={
va(e.."_load_o",1)};
t.extra_code={va(e.."_o",vi("wrdata_reg",t.offset))};
t.ackgen_code_pre={va(e.."_load_o",0)};
t.ackgen_code={va(e.."_load_o",0)};
t.reset_code_main={va(e.."_load_o",0)};
function gen_hdl_code_bit(e,a)
local t=gen_hdl_field_prefix(e,a);
e.prefix=t;
if(e.clock==nil)then
if(e.access==ACC_RW_RO)then
e.ports={port(BIT,0,"out",t.."_o","Port for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_int")};
e.acklen=1;
e.write_code={
va(t.."_int",vi("wrdata_reg",e.offset))};
e.read_code={va(vi("rddata_reg",e.offset),t.."_int")};
e.reset_code_main={va(t.."_int",csel(e.reset_value==nil,0,e.reset_value))};
e.extra_code={va(t.."_o",t.."_int")};
elseif(e.access==ACC_RO_WO)then
e.ports={port(BIT,0,"in",t.."_i","Port for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={};
e.acklen=1;
e.write_code={};
e.read_code={va(vi("rddata_reg",e.offset),t.."_i")};
e.reset_code_main={};
e.extra_code={};
elseif(e.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..e.name..")");
elseif(e.access==ACC_RW_RW)then
if(e.load==LOAD_EXT)then
e.ports={port(BIT,0,"out",t.."_o","Ports for BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG),
port(BIT,0,"in",t.."_i",nil,VPORT_REG),
port(BIT,0,"out",t.."_load_o",nil,VPORT_REG)};
e.acklen=1;
e.read_code={va(vi("rddata_reg",e.offset),t.."_i")};
e.write_code={
va(t.."_load_o",1)};
e.extra_code={va(t.."_o",vi("wrdata_reg",e.offset))};
e.ackgen_code_pre={va(t.."_load_o",0)};
e.ackgen_code={va(t.."_load_o",0)};
e.reset_code_main={va(t.."_load_o",0)};
else
die("internal RW/RW register storage unsupported yet ("..t.name..")");
die("internal RW/RW register storage unsupported yet ("..e.name..")");
end
end
else
if(t.access==ACC_RW_RO)then
t.ports={port(BIT,0,"out",e.."_o","Port for asynchronous (clock: "..t.clock..") BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={signal(BIT,0,e.."_int"),
signal(BIT,0,e.."_sync0"),
signal(BIT,0,e.."_sync1")};
t.acklen=4;
t.write_code={va(e.."_int",vi("wrdata_reg",t.offset))};
t.read_code={va(vi("rddata_reg",t.offset),e.."_int")};
t.reset_code_main={va(e.."_int",csel(t.reset_value==nil,0,t.reset_value))};
t.extra_code={vcomment("synchronizer chain for field : "..t.name.." (type RW/RO, clk_sys_i <-> "..t.clock..")");
vsyncprocess(t.clock,"rst_n_i",{
if(e.access==ACC_RW_RO)then
e.ports={port(BIT,0,"out",t.."_o","Port for asynchronous (clock: "..e.clock..") BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_int"),
signal(BIT,0,t.."_sync0"),
signal(BIT,0,t.."_sync1")};
e.acklen=4;
e.write_code={va(t.."_int",vi("wrdata_reg",e.offset))};
e.read_code={va(vi("rddata_reg",e.offset),t.."_int")};
e.reset_code_main={va(t.."_int",csel(e.reset_value==nil,0,e.reset_value))};
e.extra_code={vcomment("synchronizer chain for field : "..e.name.." (type RW/RO, clk_sys_i <-> "..e.clock..")");
vsyncprocess(e.clock,"rst_n_i",{
vreset(0,{
va(e.."_o",csel(t.reset_value==nil,0,t.reset_value));
va(e.."_sync0",csel(t.reset_value==nil,0,t.reset_value));
va(e.."_sync1",csel(t.reset_value==nil,0,t.reset_value));
va(t.."_o",csel(e.reset_value==nil,0,e.reset_value));
va(t.."_sync0",csel(e.reset_value==nil,0,e.reset_value));
va(t.."_sync1",csel(e.reset_value==nil,0,e.reset_value));
});
vposedge({
va(e.."_sync0",e.."_int");
va(e.."_sync1",e.."_sync0");
va(e.."_o",e.."_sync1");
va(t.."_sync0",t.."_int");
va(t.."_sync1",t.."_sync0");
va(t.."_o",t.."_sync1");
});
});
};
elseif(t.access==ACC_RO_WO)then
t.ports={port(BIT,0,"in",e.."_i","Port for asynchronous (clock: "..t.clock..") BIT field: '"..t.name.."' in reg: '"..a.name.."'",VPORT_REG)};
t.signals={signal(BIT,0,e.."_sync0"),
signal(BIT,0,e.."_sync1")};
t.acklen=1;
t.write_code={};
t.read_code={va(vi("rddata_reg",t.offset),e.."_sync1")};
t.reset_code_main={};
t.extra_code={vcomment("synchronizer chain for field : "..t.name.." (type RO/WO, "..t.clock.." -> clk_sys_i)");
vsyncprocess(t.clock,"rst_n_i",{
elseif(e.access==ACC_RO_WO)then
e.ports={port(BIT,0,"in",t.."_i","Port for asynchronous (clock: "..e.clock..") BIT field: '"..e.name.."' in reg: '"..a.name.."'",VPORT_REG)};
e.signals={signal(BIT,0,t.."_sync0"),
signal(BIT,0,t.."_sync1")};
e.acklen=1;
e.write_code={};
e.read_code={va(vi("rddata_reg",e.offset),t.."_sync1")};
e.reset_code_main={};
e.extra_code={vcomment("synchronizer chain for field : "..e.name.." (type RO/WO, "..e.clock.." -> clk_sys_i)");
vsyncprocess(e.clock,"rst_n_i",{
vreset(0,{
va(e.."_sync0",0);
va(e.."_sync1",0);
va(t.."_sync0",0);
va(t.."_sync1",0);
});
vposedge({
va(e.."_sync0",e.."_i");
va(e.."_sync1",e.."_sync0");
va(t.."_sync0",t.."_i");
va(t.."_sync1",t.."_sync0");
});
});
};
elseif(t.access==ACC_RW_RW)then
if(t.load~=LOAD_EXT)then
elseif(e.access==ACC_RW_RW)then
if(e.load~=LOAD_EXT)then
die("Only external load is supported for RW/RW bit fields");
end
local a="Ports for asynchronous (clock: "..t.clock..") RW/RW BIT field: '"..t.name.."' in reg: '"..a.name.."'";
t.ports={port(BIT,0,"out",e.."_o",a,VPORT_REG),
port(BIT,0,"in",e.."_i",nil,VPORT_REG),
port(BIT,0,"out",e.."_load_o",nil,VPORT_REG)};
t.signals={signal(BIT,0,e.."_int_read"),
signal(BIT,0,e.."_int_write"),
signal(BIT,0,e.."_lw"),
signal(BIT,0,e.."_lw_delay"),
signal(BIT,0,e.."_lw_read_in_progress"),
signal(BIT,0,e.."_lw_s0"),
signal(BIT,0,e.."_lw_s1"),
signal(BIT,0,e.."_lw_s2"),
signal(BIT,0,e.."_rwsel")};
t.acklen=6;
t.write_code={
va(e.."_int_write",vi("wrdata_reg",t.offset));
va(e.."_lw",1);
va(e.."_lw_delay",1);
va(e.."_lw_read_in_progress",0);
va(e.."_rwsel",1);};
t.read_code={vif(vequal("wb_we_i",0),{
va(vi("rddata_reg",t.offset),vundefined());
va(e.."_lw",1);
va(e.."_lw_delay",1);
va(e.."_lw_read_in_progress",1);
va(e.."_rwsel",0);});};
t.reset_code_main={va(e.."_lw",0);
va(e.."_lw_delay",0);
va(e.."_lw_read_in_progress",0);
va(e.."_rwsel",0);
va(e.."_int_write",0);
local a="Ports for asynchronous (clock: "..e.clock..") RW/RW BIT field: '"..e.name.."' in reg: '"..a.name.."'";
e.ports={port(BIT,0,"out",t.."_o",a,VPORT_REG),
port(BIT,0,"in",t.."_i",nil,VPORT_REG),
port(BIT,0,"out",t.."_load_o",nil,VPORT_REG)};
e.signals={signal(BIT,0,t.."_int_read"),
signal(BIT,0,t.."_int_write"),
signal(BIT,0,t.."_lw"),
signal(BIT,0,t.."_lw_delay"),
signal(BIT,0,t.."_lw_read_in_progress"),
signal(BIT,0,t.."_lw_s0"),
signal(BIT,0,t.."_lw_s1"),
signal(BIT,0,t.."_lw_s2"),
signal(BIT,0,t.."_rwsel")};
e.acklen=6;
e.write_code={
va(t.."_int_write",vi("wrdata_reg",e.offset));
va(t.."_lw",1);
va(t.."_lw_delay",1);
va(t.."_lw_read_in_progress",0);
va(t.."_rwsel",1);};
e.read_code={vif(vequal("wb_we_i",0),{
va(vi("rddata_reg",e.offset),vundefined());
va(t.."_lw",1);
va(t.."_lw_delay",1);
va(t.."_lw_read_in_progress",1);
va(t.."_rwsel",0);});};
e.reset_code_main={va(t.."_lw",0);
va(t.."_lw_delay",0);
va(t.."_lw_read_in_progress",0);
va(t.."_rwsel",0);
va(t.."_int_write",0);
};
t.ackgen_code_pre={va(e.."_lw",e.."_lw_delay");
va(e.."_lw_delay",0);
vif(vand(vequal(vi("ack_sreg",1),1),vequal(e.."_lw_read_in_progress",1)),{
va(vi("rddata_reg",t.offset),e.."_int_read");
va(e.."_lw_read_in_progress",0);
e.ackgen_code_pre={va(t.."_lw",t.."_lw_delay");
va(t.."_lw_delay",0);
vif(vand(vequal(vi("ack_sreg",1),1),vequal(t.."_lw_read_in_progress",1)),{
va(vi("rddata_reg",e.offset),t.."_int_read");
va(t.."_lw_read_in_progress",0);
});
};
t.extra_code={vcomment("asynchronous BIT register : "..t.name.." (type RW/WO, "..t.clock.." <-> clk_sys_i)");
vsyncprocess(t.clock,"rst_n_i",{
e.extra_code={vcomment("asynchronous BIT register : "..e.name.." (type RW/WO, "..e.clock.." <-> clk_sys_i)");
vsyncprocess(e.clock,"rst_n_i",{
vreset(0,{
va(e.."_lw_s0",0);
va(e.."_lw_s1",0);
va(e.."_lw_s2",0);
va(e.."_int_read",0);
va(e.."_load_o",0);
va(e.."_o",0);
va(t.."_lw_s0",0);
va(t.."_lw_s1",0);
va(t.."_lw_s2",0);
va(t.."_int_read",0);
va(t.."_load_o",0);
va(t.."_o",0);
});
vposedge({
va(e.."_lw_s0",e.."_lw");
va(e.."_lw_s1",e.."_lw_s0");
va(e.."_lw_s2",e.."_lw_s1");
vif(vand(vequal(e.."_lw_s2",0),vequal(e.."_lw_s1",1)),{
vif(vequal(e.."_rwsel",1),{
va(e.."_o",e.."_int_write");
va(e.."_load_o",1);
va(t.."_lw_s0",t.."_lw");
va(t.."_lw_s1",t.."_lw_s0");
va(t.."_lw_s2",t.."_lw_s1");
vif(vand(vequal(t.."_lw_s2",0),vequal(t.."_lw_s1",1)),{
vif(vequal(t.."_rwsel",1),{
va(t.."_o",t.."_int_write");
va(t.."_load_o",1);
},{
va(e.."_load_o",0);
va(e.."_int_read",e.."_i");
va(t.."_load_o",0);
va(t.."_int_read",t.."_i");
});
},{
va(e.."_load_o",0);
va(t.."_load_o",0);
});
});
});
};
elseif(t.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..t.name..")");
elseif(e.access==ACC_WO_RO)then
die("WO-RO type unsupported yet ("..e.name..")");
end
end
end
......@@ -3506,7 +3618,7 @@ end
if(e.__type==TYPE_RAM)then
gen_code_ram(e);
else
foreach_subfield(e,function(t,e)gen_hdl_code_reg_field(t,e);end);
foreach_subfield(e,function(e,t)gen_hdl_code_reg_field(e,t);end);
end
end
function gen_hdl_block_select_bits()
......@@ -3627,7 +3739,7 @@ signal(BIT,0,"eic_ier_write_int");};
["extra_code"]={va(vi("eic_ier_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true;
};
local a={["__type"]=TYPE_REG;
local o={["__type"]=TYPE_REG;
["__blockindex"]=1000002;
["align"]=1;
["name"]="Interrupt status register";
......@@ -3646,7 +3758,7 @@ signal(BIT,0,"eic_isr_write_int");};
["extra_code"]={va(vi("eic_isr_clear_int",periph.irqcount-1,0),vi("wrdata_reg",periph.irqcount-1,0));};
["no_std_regbank"]=true;
};
local o={["__type"]=TYPE_REG;
local a={["__type"]=TYPE_REG;
["__blockindex"]=1000003;
["align"]=1;
["name"]="Interrupt mask register";
......@@ -3674,7 +3786,7 @@ local t={
["access_bus"]=READ_WRITE;
["access_dev"]=READ_WRITE;
};
local n={
local h={
["__blockindex"]=e.index;
["__type"]=TYPE_FIELD;
["type"]=BIT;
......@@ -3685,7 +3797,7 @@ local n={
["access_bus"]=WRITE_ONLY;
["access_dev"]=READ_ONLY;
};
local r={
local n={
["__blockindex"]=e.index;
["__type"]=TYPE_FIELD;
["type"]=BIT;
......@@ -3696,7 +3808,7 @@ local r={
["access_bus"]=WRITE_ONLY;
["access_dev"]=READ_ONLY;
};
local h={
local r={
["__blockindex"]=e.index;
["__type"]=TYPE_FIELD;
["type"]=BIT;
......@@ -3716,18 +3828,18 @@ end
if(e.mask_line==true)then
table_join(e.ports,{port(BIT,0,"out",e.full_prefix.."_mask_o");});
end
table.insert(s,r);
table.insert(a,t);
table.insert(o,h);
table.insert(i,n);
table.insert(s,n);
table.insert(o,t);
table.insert(a,r);
table.insert(i,h);
end);
add_global_signals({
signal(SLV,periph.irqcount,"irq_inputs_vector_int");
});
table.insert(periph,s);
table.insert(periph,i);
table.insert(periph,o);
table.insert(periph,a);
table.insert(periph,o);
local e={vgm("g_num_interrupts",periph.irqcount);
vpm("clk_i","clk_sys_i");
vpm("rst_n_i","rst_n_i");
......@@ -3743,12 +3855,12 @@ vpm("reg_isr_i","eic_isr_clear_int");
vpm("reg_isr_wr_stb_i","eic_isr_write_int");
vpm("wb_irq_o","wb_int_o");
};
local a;
for o,t in ipairs(n)do
table_join(e,{vgm(string.format("g_irq%02x_mode",t.index),t.trigger)});
a=o;
local t;
for o,a in ipairs(n)do
table_join(e,{vgm(string.format("g_irq%02x_mode",a.index),a.trigger)});
t=o;
end
for t=a,31 do
for t=t,31 do
table_join(e,{vgm(string.format("g_irq%02x_mode",t),0)});
end
local t={vinstance("eic_irq_controller_inst","wbgen2_eic",e);};
......@@ -3924,20 +4036,20 @@ local s={
["hdl_prefix"]=e.hdl_prefix.."_CSR";
["no_std_regbank"]=true;
};
function gen_fifo_csr_field(d,n,t,a,h,o,r,i)
function gen_fifo_csr_field(a,n,t,r,h,o,d,i)
if(e.flags_bus==nil)then
return;
end
if inset(d,e.flags_bus)then
if inset(a,e.flags_bus)then
local t={
["__type"]=TYPE_FIELD;
["name"]=t;
["description"]=a;
["description"]=r;
["access_bus"]=READ_ONLY;
["access_dev"]=WRITE_ONLY;
["type"]=o;
["size"]=h;
["offset"]=r;
["offset"]=d;
["c_prefix"]=n;
["hdl_prefix"]=n;
["signals"]={};
......@@ -4134,8 +4246,8 @@ foreach_reg(ALL_REG_TYPES,function(e)
gen_abstract_code(e);
end);
local i={};
local n={};
local o={};
local n={};
foreach_field(function(e,t)
table_join(i,e.reset_code_main);
end);
......@@ -4144,11 +4256,11 @@ table_join(i,e.reset_code_main);
end);
foreach_reg({TYPE_REG},function(e)
foreach_subfield(e,function(e,t)
table_join(n,e.ackgen_code);
table_join(o,e.ackgen_code_pre);
table_join(o,e.ackgen_code);
table_join(n,e.ackgen_code_pre);
end);
table_join(n,e.ackgen_code);
table_join(o,e.ackgen_code_pre);
table_join(o,e.ackgen_code);
table_join(n,e.ackgen_code_pre);
end);
local e={};
foreach_reg({TYPE_REG},function(t)
......@@ -4232,7 +4344,7 @@ vcomment("advance the ACK generator shift register");
va(vi("ack_sreg",MAX_ACK_LENGTH-2,0),vi("ack_sreg",MAX_ACK_LENGTH-1,1));
va(vi("ack_sreg",MAX_ACK_LENGTH-1),0);
vif(vequal("ack_in_progress",1),{
vif(vequal(vi("ack_sreg",0),1),{n;va("ack_in_progress",0);},o);
vif(vequal(vi("ack_sreg",0),1),{o;va("ack_in_progress",0);},n);
},{
e
});
......@@ -4302,7 +4414,7 @@ va("wb_ack_o",vi("ack_sreg",0));
});
return e;
end
wbgen2_version="0.7.0-alpha"
wbgen2_version="0.7.0-epics"
options={};
options.reset_type="asynchronous";
options.target_interconnect="wb-classic";
......@@ -4318,6 +4430,7 @@ local t=[[options:
-C, --co=FILE Write the slave's generated C header file to FILE
-f, --docformat=FORMAT Write documentation for latex, texinfo or HTML (defaults to HTML)
-D, --doco=FILE Write the slave's generated documentation to FILE
-E, --epicsdb=FILE Write the slave's generated epics db FILE
-h, --help Show this help text
-l, --lang=LANG Set the output Hardware Description Language (HDL) to LANG
Valid values for LANG: {vhdl,verilog}
......@@ -4340,13 +4453,14 @@ function usage_complete()
print(e)
print(t)
end
function parse_args(a)
function parse_args(o)
local t={
help="h",
version="v",
co="C",
docformat="f",
doco="D",
epicsdb="E",
constco="K",
lang="l",
vo="V",
......@@ -4355,8 +4469,8 @@ cstyle="s",
hstyle="H"
}
local e
local o
e,o=alt_getopt.get_opts(a,"hvC:D:K:l:V:s:f:H:p:",t)
local a
e,a=alt_getopt.get_opts(o,"hvC:D:E:K:l:V:s:f:H:p:",t)
for t,e in pairs(e)do
if t=="h"then
usage_complete()
......@@ -4368,6 +4482,8 @@ elseif t=="C"then
options.output_c_header_file=e
elseif t=="D"then
options.output_doc_file=e
elseif t=="E"then
options.output_epics_db_file=e
elseif t=="K"then
options.output_vlog_constants_file=e
elseif t=="f"then
......@@ -4393,11 +4509,11 @@ end
options.hdl_reg_style=e
end
end
if(a[o]==nil)then
if(o[a]==nil)then
usage()
os.exit(0)
end
input_wb_file=a[o];
input_wb_file=o[a];
end
parse_args(arg);
dofile(input_wb_file);
......@@ -4437,6 +4553,11 @@ cgen_generate_init(options.output_c_header_file)
cgen_generate_c_header_code();
cgen_generate_done();
end
if(options.output_epics_db_file~=nil)then
cgen_generate_init(options.output_epics_db_file)
cgen_generate_epics_db_code();
cgen_generate_done();
end
if(options.output_vlog_constants_file~=nil)then
cgen_gen_vlog_constants(options.output_vlog_constants_file);
end
......
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