Commit f8ead30c authored by twlostow's avatar twlostow

fixed ohwr bug #99

git-svn-id: http://svn.ohwr.org/wishbone-gen@21 4537843c-45c2-4d80-8546-c3283569414f
parent a399be75
......@@ -2596,8 +2596,8 @@ t.ackgen_code_pre={va(e.."_lw",e.."_lw_delay");
va(e.."_lw_delay",0);
vif(vand(vequal(vi("ack_sreg",1),1),vequal(e.."_lw_read_in_progress",1)),{
va(vir("rddata_reg",t),e.."_int_read");
});
va(e.."_lw_read_in_progress",0);
});
};
t.extra_code={vcomment("asynchronous "..fieldtype_2_vhdl[t.type].." register : "..t.name.." (type RW/WO, "..t.clock.." <-> bus_clock_int)");
vsyncprocess(t.clock,"rst_n_i",{
......
......@@ -522,8 +522,8 @@ function gen_hdl_code_slv(field, reg)
va(prefix.."_lw_delay", 0);
vif (vand(vequal(vi("ack_sreg", 1), 1), vequal(prefix.."_lw_read_in_progress", 1)), {
va(vir("rddata_reg", field), prefix.."_int_read");
va(prefix.."_lw_read_in_progress", 0);
});
va(prefix.."_lw_read_in_progress", 0);
};
field.extra_code = { vcomment("asynchronous "..fieldtype_2_vhdl[field.type].." register : "..field.name.." (type RW/WO, "..field.clock.." <-> bus_clock_int)");
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment