- 15 Jun, 2017 1 commit
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Dimitris Lampridis authored
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- 14 Jun, 2017 1 commit
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Dimitris Lampridis authored
For now, the access from the bus is RW, we need to define a new RO/RO mode in wbgen.
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- 27 Apr, 2017 1 commit
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Dimitris Lampridis authored
target_pipelined_wb: in case of an if-generate, also add a second (complementary) if-generate to drive all outputs when the if-generate condition is false
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- 28 Aug, 2015 1 commit
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Federico Vaga authored
Signed-off-by: Federico Vaga <federico.vaga@gmail.com> Signed-off-by: Tomasz Włostowski <tomasz.wlostowski@cern.ch>
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- 07 Feb, 2014 1 commit
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Tomasz Wlostowski authored
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- 04 Dec, 2013 2 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 12 Nov, 2013 1 commit
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Tomasz Wlostowski authored
cgen_vhdl: fixed f_x_to_zero() function in generated VHDL package causing synthesis error on Mentor Precision
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- 09 Sep, 2013 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 04 Jul, 2013 1 commit
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Tomasz Wlostowski authored
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- 25 Apr, 2013 1 commit
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Tomasz Wlostowski authored
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- 19 Apr, 2013 4 commits
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
initial support for 'optional' parameter (conditional instantiation of RAMs and FIFOs depending on a user-defined generic value)
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- 05 Apr, 2013 1 commit
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Tomasz Wlostowski authored
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- 12 Feb, 2013 1 commit
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Tomasz Wlostowski authored
fixed readback value of write-only (monostable) bits to 0. See Wesley's message on white-rabbit-dev, dated 12/02/2013 for explanation
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- 28 Jan, 2013 1 commit
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Tomasz Wlostowski authored
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- 05 Dec, 2012 1 commit
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Tomasz Wlostowski authored
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- 25 Oct, 2012 1 commit
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Tomasz Wlostowski authored
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- 17 Jul, 2012 3 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 26 Jun, 2012 7 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 24 Oct, 2011 2 commits
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twlostow authored
git-svn-id: http://svn.ohwr.org/wishbone-gen@27 4537843c-45c2-4d80-8546-c3283569414f
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twlostow authored
VHDL code generator: use separate records for in and out registers to avoid problems with tristate2logic in XIlinx tools git-svn-id: http://svn.ohwr.org/wishbone-gen@26 4537843c-45c2-4d80-8546-c3283569414f
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- 30 May, 2011 3 commits
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twlostow authored
git-svn-id: http://svn.ohwr.org/wishbone-gen@25 4537843c-45c2-4d80-8546-c3283569414f
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twlostow authored
git-svn-id: http://svn.ohwr.org/wishbone-gen@24 4537843c-45c2-4d80-8546-c3283569414f
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twlostow authored
git-svn-id: http://svn.ohwr.org/wishbone-gen@23 4537843c-45c2-4d80-8546-c3283569414f
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- 15 Nov, 2010 1 commit
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twlostow authored
git-svn-id: http://svn.ohwr.org/wishbone-gen@22 4537843c-45c2-4d80-8546-c3283569414f
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- 07 Oct, 2010 1 commit
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twlostow authored
git-svn-id: http://svn.ohwr.org/wishbone-gen@21 4537843c-45c2-4d80-8546-c3283569414f
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- 06 Aug, 2010 1 commit
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twlostow authored
git-svn-id: http://svn.ohwr.org/wishbone-gen@20 4537843c-45c2-4d80-8546-c3283569414f
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- 05 Jul, 2010 1 commit
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twlostow authored
git-svn-id: http://svn.ohwr.org/wishbone-gen@19 4537843c-45c2-4d80-8546-c3283569414f
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