Commits · cea56bbe5f85b03de619a75e7445cc821a64d7d7 · Projects / Wishbone slave generator

04 Dec, 2013 2 commits
- fixed zero-alignment bug 1st field in the register · cea56bbe
  Tomasz Wlostowski authored Dec 04, 2013
  
  cea56bbe
- add reset_value parameter for SLVs and asynchronously clocked bits/SLVs · 4aea82ba
  Tomasz Wlostowski authored Dec 04, 2013
  
  4aea82ba
12 Nov, 2013 1 commit
- cgen_vhdl: fixed f_x_to_zero() function in generated VHDL package causing… · a4515fff
  Tomasz Wlostowski authored Nov 12, 2013
```
cgen_vhdl: fixed f_x_to_zero() function in generated VHDL package causing synthesis error on Mentor Precision
```
  a4515fff
09 Sep, 2013 2 commits
- cgen_doc_latex: add \hline at the end of Mem Map Summary table · 09fa8c89
  Grzegorz Daniluk authored Sep 09, 2013
  
  09fa8c89
- cgen_doc_latex: print SW Offset instead of HW Addr in Memory Map Summary · 7f405392
  Grzegorz Daniluk authored Sep 09, 2013
  
  7f405392
04 Jul, 2013 1 commit
- texinfo doc generator: don't produce empty field-description tables if no descriptions are provided · 8fbd2914
  Tomasz Wlostowski authored Jul 04, 2013
  
  8fbd2914
25 Apr, 2013 1 commit
- fixed (again) wrong HTML documentation generator function name · b4edc693
  Tomasz Wlostowski authored Apr 25, 2013
  
  b4edc693
19 Apr, 2013 4 commits
- updated squished binary · 7f478544
  Tomasz Wlostowski authored Apr 19, 2013
  
  7f478544
- adding generation of Latex docs · f4b155be
  Grzegorz Daniluk authored Apr 19, 2013
  
  f4b155be
- fix html doc generation, wrong function name · 6649e3f0
  Grzegorz Daniluk authored Mar 27, 2013
  
  6649e3f0
- initial support for 'optional' parameter (conditional instantiation of RAMs and… · bbeb98a0
  Tomasz Wlostowski authored Apr 19, 2013
```
initial support for 'optional' parameter (conditional instantiation of RAMs and FIFOs depending on a user-defined generic value)
```
  bbeb98a0
05 Apr, 2013 1 commit
- fixed HTML documentaion generation crash · 490a61cc
  Tomasz Wlostowski authored Apr 05, 2013
  
  490a61cc
12 Feb, 2013 1 commit
- fixed readback value of write-only (monostable) bits to 0. See Wesley's message… · 93e0e4f4
  Tomasz Wlostowski authored Feb 12, 2013
```
fixed readback value of write-only (monostable) bits to 0. See Wesley's message on white-rabbit-dev, dated 12/02/2013 for explanation
```
  93e0e4f4
28 Jan, 2013 1 commit
- TexInfo doc: use macro to define sections/subsections/chapters · 50e10c5b
  Tomasz Wlostowski authored Jan 28, 2013
  
  50e10c5b
05 Dec, 2012 1 commit
- added reset value option (single-bit registers only, wip) · 2113b3eb
  Tomasz Wlostowski authored Dec 05, 2012
  
  2113b3eb
25 Oct, 2012 1 commit
- added texinfo documentation target (unfinished) · 4bc4cbc9
  Tomasz Wlostowski authored Oct 25, 2012
  
  4bc4cbc9
17 Jul, 2012 3 commits
- wbgen_main: use pipelined code generator · a0b44645
  Tomasz Wlostowski authored Jul 17, 2012
  
  a0b44645
- added pipelined wishbone target · 52e1a315
  Tomasz Wlostowski authored Jul 17, 2012
  
  52e1a315
- wbgen_regbank.lua: avoid clock line assignments causing simulation errors · 51d29598
  Tomasz Wlostowski authored Jul 17, 2012
  
  51d29598
26 Jun, 2012 7 commits
- wbgen_rams.lua: fixed clock net name · c6850dc6
  Tomasz Wlostowski authored Jun 26, 2012
  
  c6850dc6
- wbgen_fifos.lua: added FIFO clear signal (both host/device driven) · bb962cb4
  Tomasz Wlostowski authored Jun 26, 2012
  
  bb962cb4
- wbgen_eic.lua: rename clock/interrupt net names · 623b91de
  Tomasz Wlostowski authored Jun 26, 2012
  
  623b91de
- wbgen_common.lua: more checks · 2476a8d6
  Tomasz Wlostowski authored Jun 26, 2012
  
  2476a8d6
- VHDL code generator · 369a3a29
  Tomasz Wlostowski authored Jun 26, 2012
  
  369a3a29
- common: added vor operator, fixed RAM defines generation for verilog · 806e1215
  Tomasz Wlostowski authored Jun 26, 2012
  
  806e1215
- C headers : add RAM base address define · 9c7e6c41
  Tomasz Wlostowski authored Jun 26, 2012
  
  9c7e6c41
24 Oct, 2011 2 commits

added dummy read register assignment during read of MONOSTABLE fields · 04a79f31
twlostow authored Oct 24, 2011
```
git-svn-id: http://svn.ohwr.org/wishbone-gen@27 4537843c-45c2-4d80-8546-c3283569414f
```
04a79f31

VHDL code generator: use separate records for in and out registers to avoid… · 15081e0b

twlostow authored Oct 24, 2011

VHDL code generator: use separate records for in and out registers to avoid problems with tristate2logic in XIlinx tools

git-svn-id: http://svn.ohwr.org/wishbone-gen@26 4537843c-45c2-4d80-8546-c3283569414f

15081e0b

30 May, 2011 3 commits
- updated version info · cbfb2599
  twlostow authored May 30, 2011
```
git-svn-id: http://svn.ohwr.org/wishbone-gen@25 4537843c-45c2-4d80-8546-c3283569414f
```
  cbfb2599
- added support for wrapping VHDL registers fields in a RECORD · de40961e
  twlostow authored May 30, 2011
```
git-svn-id: http://svn.ohwr.org/wishbone-gen@24 4537843c-45c2-4d80-8546-c3283569414f
```
  de40961e
- HDL library: now uses general-cores (genrams) to instantiate RAM/FIFO primitives · a281a99c
  twlostow authored May 30, 2011
```
git-svn-id: http://svn.ohwr.org/wishbone-gen@23 4537843c-45c2-4d80-8546-c3283569414f
```
  a281a99c
15 Nov, 2010 1 commit
- bugfixes in FIFO generator, added read notifications · 72a0f7f0
  twlostow authored Nov 15, 2010
```
git-svn-id: http://svn.ohwr.org/wishbone-gen@22 4537843c-45c2-4d80-8546-c3283569414f
```
  72a0f7f0
07 Oct, 2010 1 commit

fixed ohwr bug #99 · f8ead30c

twlostow authored Oct 07, 2010

git-svn-id: http://svn.ohwr.org/wishbone-gen@21 4537843c-45c2-4d80-8546-c3283569414f

f8ead30c

06 Aug, 2010 1 commit

x · a399be75

twlostow authored Aug 06, 2010

git-svn-id: http://svn.ohwr.org/wishbone-gen@20 4537843c-45c2-4d80-8546-c3283569414f

a399be75

05 Jul, 2010 1 commit
- fixed 'load' signal bug in SLV-type RW/RW registers · d20fa15c
  twlostow authored Jul 05, 2010
```
git-svn-id: http://svn.ohwr.org/wishbone-gen@19 4537843c-45c2-4d80-8546-c3283569414f
```
  d20fa15c
18 Jun, 2010 1 commit
- bugfix: VHDL code error in case() statement generation for <3 cases · 54091524
  twlostow authored Jun 18, 2010
```
git-svn-id: http://svn.ohwr.org/wishbone-gen@18 4537843c-45c2-4d80-8546-c3283569414f
```
  54091524
15 Jun, 2010 1 commit
- Added CONSTANT registers & #define REGISTER_ADDRESS macros in C code generator · dcd6b1f9
  twlostow authored Jun 15, 2010
```
git-svn-id: http://svn.ohwr.org/wishbone-gen@17 4537843c-45c2-4d80-8546-c3283569414f
```
  dcd6b1f9
02 Jun, 2010 1 commit
- Added field offset/masks defines for verilog constant file generator · 69763cad
  twlostow authored Jun 02, 2010
```
git-svn-id: http://svn.ohwr.org/wishbone-gen@16 4537843c-45c2-4d80-8546-c3283569414f
```
  69763cad
01 Jun, 2010 1 commit
- Fixed a bug in remove_duplicates() causing missing clocks in entity port list · 6f94346b
  twlostow authored Jun 01, 2010
```
git-svn-id: http://svn.ohwr.org/wishbone-gen@15 4537843c-45c2-4d80-8546-c3283569414f
```
  6f94346b
26 May, 2010 1 commit

Fixed EIC generation bug (invalid VHDL when there is only 1 interrupts), added… · 8616b045

twlostow authored May 26, 2010

Fixed EIC generation bug (invalid VHDL when there is only 1 interrupts), added support for asynchronous FIFOs

git-svn-id: http://svn.ohwr.org/wishbone-gen@14 4537843c-45c2-4d80-8546-c3283569414f

8616b045