1. 04 May, 2018 1 commit
  2. 18 Apr, 2018 2 commits
    • Dimitris Lampridis's avatar
      Partially revert cc5a5c00. · 53807e02
      Dimitris Lampridis authored
      Some of the signals dropped in commit cc5a5c00 were actually being used when generating RAMs.
      
      They have been reintroduced, but this time only when generating RAMs.
      53807e02
    • Tomasz Wlostowski's avatar
      final updates to wbgen2 before it gets replaced by Cheby: · 6ee9c2e0
      Tomasz Wlostowski authored
      - record_full interface option: use general cores's library WB interface types
        to simplify connection of the cores. Enabled by -H record_full option
      - use byte addressing for WB address (in record_full mode)
      - allow specifying package name with record/component definitions (hdl_package field in the peripheral record)
      - fixed indentation & formatting of produced VHDL package files
      - include VHDL component declaration in the package files
      6ee9c2e0
  3. 15 Jun, 2017 1 commit
  4. 27 Apr, 2017 1 commit
  5. 19 Apr, 2013 1 commit
  6. 17 Jul, 2012 1 commit
  7. 30 May, 2011 1 commit
  8. 07 May, 2010 1 commit
  9. 27 Apr, 2010 1 commit
  10. 03 Apr, 2010 1 commit
  11. 29 Mar, 2010 1 commit