RAM access mode
When generating a RAM with access modes other than READ_WRITE on both sides, I get the error:
Error: cgen internal error: undefined signal 'XXX_wr_int' make: *** [XXX] Error 255
When generating a RAM with access modes other than READ_WRITE on both sides, I get the error:
Error: cgen internal error: undefined signal 'XXX_wr_int' make: *** [XXX] Error 255