read_first conflict resolution not compatible with Altera generic_dpsram.vhdl
I am using Quartus Prime Lite 16.1.2, latest git versions from
wishbone-gen and general-cores.
In lib/wbgen2_dpssram.vhd
generic_dpram is instantiated with
g_addr_conflict_resolution : string := "read_first";
. When
synthesizing using the file modules/genrams/altera/generic_dpram.vhd
from general-cores I get an
assertion:
Error (10652): VHDL Assertion Statement at generic_dpram.vhd(128): assertion is false - report "generic_dpram: read_first is only possible when dual_clock is false" (FAILURE or ERROR)
Error (12152): Can't elaborate user hierarchy "mcu_ram:RAM|wbgen2_dpssram:ram_core_raminst|generic_dpram:wrapped_dpram"
This is solved by changing to g_addr_conflict_resolution : string := "dont_care";