Peripheral block
Peripheral* block contains a single Wishbone peripheral. It's the
main (top-level) block in each WB file. Peripheral block may contain any
number
of registers, FIFO registers, RAMs and up to 32 interrupt request lines.
Block-specific attributes
Attribute | Status | Description |
---|---|---|
hdl_entity | mandatory | Name of the VHDL entity or Verilog module of the slave core to be generated. |
Example code
<code class="C">
peripheral {
name = "Wishbone GPIO port"; -- short, human-readable peripheral name
description = "A longer description of the GPIO port. A GPIO port\
is an interface between I/O pins and CPU which ...... Lorem ipsum dolor sit amet...";
hdl_entity = "wishbone_gpio_port_slave"; -- name of the entity to be generated
c_prefix = "GPIO"; -- prefix of all names (memories, registers, etc.) in C header file.
hdl_prefix = "GPIO"; -- prefix of all port names in VHDL/Verilog file.
reg { -- a register definition.
name = "Pin status register";
prefix = "PSR";
-- .... more attributes
};
};
</code>