--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 8.3 Revision 5 from HDL Works B.V.
--
-- Ease library  : design
-- HDL library   : work
-- Host name     : SERING
-- User name     : peterj
-- Time stamp    : Thu Mar 23 12:10:08 2017
--
-- Designed by   : 
-- Company       : 
-- Project info  : 
--
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
-- Object        : Entity design.clb_wrpc
-- Last modified : Thu Mar 23 12:08:05 2017
--------------------------------------------------------------------------------



library ieee, work, unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wrcore_pkg.all;
use work.softpll_pkg.all;
use unisim.VCOMPONENTS.all;

entity clb_wrpc is
  generic(
    g_simulation  : integer := 0;
    g_dpram_size  : integer := 90112/4;
    g_dpram_initf : string := "");
  port (
    LED_ACT              : out    std_logic;
    LED_LINK             : out    std_logic;
    bitslide             : out    std_logic_vector(4 downto 0);
    button1_i            : in     std_logic;
    button2_i            : in     std_logic;
    clk20_vcxo           : in     std_logic;
    clk_ext_i            : in     std_logic := '0';
    clk_ext_mul_i        : in     std_logic := '0';
    clk_ext_mul_locked_i : in     std_logic := '1';
    clk_gtx_i            : in     std_logic;
    clk_sys_i            : in     std_logic;
    dac_cs1_n_o          : out    std_logic;
    dac_cs2_n_o          : out    std_logic;
    dac_din_o            : out    std_logic;
    dac_sclk_o           : out    std_logic;
    dio_led_bot_o        : out    std_logic;
    dio_led_top_o        : out    std_logic;
    dio_onewire_b        : inout  std_logic;
    fc_pause_ack_o       : out    std_logic;
    fc_pause_delay_i     : in     std_logic_vector(15 downto 0);
    fc_pause_p_i         : in     std_logic;
    fpga_scl_b           : inout  std_logic;
    fpga_sda_b           : inout  std_logic;
    pps_ext_i            : in     std_logic := '0';
    pps_o                : out    std_logic;
    ref_clk_locked_o     : out    std_logic;
    ref_clk_o            : out    std_logic;
    rx_rbclk_o           : out    std_logic;
    rxts_o               : out    std_logic;
    sfp_los_i            : in     std_logic;
    sfp_mod_def0_b       : in     std_logic;
    sfp_mod_def1_b       : inout  std_logic;
    sfp_mod_def2_b       : inout  std_logic;
    sfp_rate_select_b    : inout  std_logic;
    sfp_rxn_i            : in     std_logic;
    sfp_rxp_i            : in     std_logic;
    sfp_tx_disable_o     : out    std_logic;
    sfp_tx_fault_i       : in     std_logic;
    sfp_txn_o            : out    std_logic;
    sfp_txp_o            : out    std_logic;
    thermo_id            : inout  std_logic;
    tm_cycles_o          : out    std_logic_vector(27 downto 0);
    tm_tai_o             : out    std_logic_vector(39 downto 0);
    tm_time_valid_o      : out    std_logic;
    txts_o               : out    std_logic;
    uart_rxd_i           : in     std_logic;
    uart_txd_o           : out    std_logic;
    wb_bridge_master_i   : in     t_wishbone_master_in;
    wb_bridge_master_o   : out    t_wishbone_master_out;
    wb_bridge_slave_i    : in     t_wishbone_slave_in;
    wb_bridge_slave_o    : out    t_wishbone_slave_out;
    wrf_snk_i            : in     t_wrf_sink_in := c_dummy_snk_in;
    wrf_snk_o            : out    t_wrf_sink_out;
    wrf_src_i            : in     t_wrf_source_in := c_dummy_src_in;
    wrf_src_o            : out    t_wrf_source_out);
end entity clb_wrpc;

--------------------------------------------------------------------------------
-- Object        : Architecture design.clb_wrpc.structure
-- Last modified : Thu Mar 23 12:08:05 2017
--------------------------------------------------------------------------------

architecture structure of clb_wrpc is

  signal local_reset_n_d0: std_logic;
  signal local_reset_n_d1: std_logic;
  signal clk_dmtd           : std_ulogic;
  signal local_reset_n      : std_logic;
  signal phy_tx_data_o      : std_logic_vector(f_pcs_data_width(true)-1 downto 0);
  signal ch1_tx_disparity_o : std_logic;
  signal ch1_tx_enc_err_o   : std_logic;
  signal ch1_rx_enc_err_o   : std_logic;
  signal bitslide_net       : std_logic_vector(4 downto 0);
  signal dac_cs_n_o         : std_logic_vector(1 downto 0);
  signal dac_hpll_data_o    : std_logic_vector(15 downto 0);
  signal dac_hpll_load_p1_o : std_logic;
  signal dac_dpll_load_p1_o : std_logic;
  signal dac_dpll_data_o    : std_logic_vector(15 downto 0);
  signal wrc_scl_o          : std_logic;
  signal wrc_scl_i          : std_logic;
  signal wrc_sda_o          : std_logic;
  signal wrc_sda_i          : std_logic;
  signal sfp_scl_o          : std_logic;
  signal sfp_scl_i          : std_logic;
  signal sfp_sda_o          : std_logic;
  signal sfp_sda_i          : std_logic;
  signal owr_en             : std_logic_vector(1 downto 0);
  signal owr_i              : std_logic_vector(1 downto 0);
  signal pps_led            : std_logic;
  signal pllout_clk_dmtd    : std_logic;
  signal u3_CLKFBOUT        : std_ulogic := '0';
  signal phy_rst_o          : std_logic;
  signal rx_data_o          : std_logic_vector(15 downto 0);
  signal rx_rbclk_o_net     : std_logic;
  signal ref_clk_o_net      : std_logic;
  signal phy_loopen_o       : std_logic_vector(2 downto 0);
  signal tx_prbs_sel        : std_logic_vector(2 downto 0);
  signal phy_tx_k_o         : std_logic_vector(1 downto 0);
  signal rx_k_o             : std_logic_vector(1 downto 0);
  signal rdy_o              : std_logic;

  component spec_serial_dac_arb
    generic(
      g_invert_sclk    : boolean;
      g_num_extra_bits : integer);
    port (
      clk_i       : in     std_logic;
      rst_n_i     : in     std_logic;
      val1_i      : in     std_logic_vector(15 downto 0);
      load1_i     : in     std_logic;
      val2_i      : in     std_logic_vector(15 downto 0);
      load2_i     : in     std_logic;
      dac_cs_n_o  : out    std_logic_vector(1 downto 0);
      dac_clr_n_o : out    std_logic;
      dac_sclk_o  : out    std_logic;
      dac_din_o   : out    std_logic);
  end component spec_serial_dac_arb;

  component wr_gtx_phy_family7
    generic(
      g_simulation : integer := 0);
    port (
      clk_gtx_i      : in     std_logic;
      tx_out_clk_o   : out    std_logic;
      tx_locked_o    : out    std_logic;
      tx_data_i      : in     std_logic_vector(15 downto 0);
      tx_k_i         : in     std_logic_vector(1 downto 0);
      tx_disparity_o : out    std_logic;
      tx_enc_err_o   : out    std_logic;
      rx_rbclk_o     : out    std_logic;
      rx_data_o      : out    std_logic_vector(15 downto 0);
      rx_k_o         : out    std_logic_vector(1 downto 0);
      rx_enc_err_o   : out    std_logic;
      rx_bitslide_o  : out    std_logic_vector(4 downto 0);
      rst_i          : in     std_logic;
      loopen_i       : in     std_logic_vector(2 downto 0);
      tx_prbs_sel_i  : in     std_logic_vector(2 downto 0);
      pad_txn_o      : out    std_logic;
      pad_txp_o      : out    std_logic;
      pad_rxn_i      : in     std_logic := '0';
      pad_rxp_i      : in     std_logic := '0';
      rdy_o          : out    std_logic);
  end component wr_gtx_phy_family7;

begin
  --Source and Sink ports:
  --All non PTP packets
  --BitSlide can be connected to GPIO_LEDs
  --for debugging purposes
  --Bridge from LM32_2nd to WRPC 
  --(WRPC = "Slave")
  --Bridge from WRPC to LM32_2nd
  --(WRPC = "Master")
  --loopen_i determines (7 Series Transceiver User Guide(UG476) Figure 2-23 and Table 2-37):
  --'0' => gtx_loopback = "000" => normal operation
  --'1' => gtx_loopback = "100" => Far-end PMA Loopback
  --
  dio_led_bot_o <= '0';
  bitslide <= "00000";
  dac_cs2_n_o <= dac_cs_n_o(1);
  dac_cs1_n_o <= dac_cs_n_o(0);
  dio_led_top_o <= pps_led;
  rx_rbclk_o <= rx_rbclk_o_net;
  ref_clk_o <= ref_clk_o_net;

  cmp_clk_dmtd_buf: BUFG
    port map(
      O => clk_dmtd,
      I => pllout_clk_dmtd);

  U_DAC_ARB: spec_serial_dac_arb
    generic map(
      g_invert_sclk    => FALSE,
      g_num_extra_bits => 8)
    port map(
      clk_i       => clk_sys_i,
      rst_n_i     => local_reset_n,
      val1_i      => dac_dpll_data_o,
      load1_i     => dac_dpll_load_p1_o,
      val2_i      => dac_hpll_data_o,
      load2_i     => dac_hpll_load_p1_o,
      dac_cs_n_o  => dac_cs_n_o,
      dac_clr_n_o => open,
      dac_sclk_o  => dac_sclk_o,
      dac_din_o   => dac_din_o);

  u3: MMCME2_ADV
    generic map(
      BANDWIDTH            => "OPTIMIZED",
      CLKFBOUT_MULT_F      => 50.000,
      CLKFBOUT_PHASE       => 0.000,
      CLKFBOUT_USE_FINE_PS => FALSE,
      CLKIN1_PERIOD        => 50.000,
      CLKIN2_PERIOD        => 0.0,
      CLKOUT0_DIVIDE_F     => 16.000,
      CLKOUT0_DUTY_CYCLE   => 0.500,
      CLKOUT0_PHASE        => 0.0,
      CLKOUT0_USE_FINE_PS  => FALSE,
      CLKOUT1_DIVIDE       => 16,
      CLKOUT1_DUTY_CYCLE   => 0.500,
      CLKOUT1_PHASE        => 0.00,
      CLKOUT1_USE_FINE_PS  => FALSE,
      CLKOUT2_DIVIDE       => 1,
      CLKOUT2_DUTY_CYCLE   => 0.5,
      CLKOUT2_PHASE        => 0.0,
      CLKOUT2_USE_FINE_PS  => FALSE,
      CLKOUT3_DIVIDE       => 1,
      CLKOUT3_DUTY_CYCLE   => 0.5,
      CLKOUT3_PHASE        => 0.0,
      CLKOUT3_USE_FINE_PS  => FALSE,
      CLKOUT4_CASCADE      => FALSE,
      CLKOUT4_DIVIDE       => 1,
      CLKOUT4_DUTY_CYCLE   => 0.5,
      CLKOUT4_PHASE        => 0.0,
      CLKOUT4_USE_FINE_PS  => FALSE,
      CLKOUT5_DIVIDE       => 1,
      CLKOUT5_DUTY_CYCLE   => 0.5,
      CLKOUT5_PHASE        => 0.0,
      CLKOUT5_USE_FINE_PS  => FALSE,
      CLKOUT6_DIVIDE       => 1,
      CLKOUT6_DUTY_CYCLE   => 0.5,
      CLKOUT6_PHASE        => 0.0,
      CLKOUT6_USE_FINE_PS  => FALSE,
      COMPENSATION         => "ZHOLD",
      DIVCLK_DIVIDE        => 1,
      REF_JITTER1          => 0.010,
      REF_JITTER2          => 0.0,
      SS_EN                => "FALSE",
      SS_MODE              => "CENTER_HIGH",
      SS_MOD_PERIOD        => 10000,
      STARTUP_WAIT         => FALSE)
    port map(
      CLKFBOUT     => u3_CLKFBOUT,
      CLKFBOUTB    => open,
      CLKFBSTOPPED => open,
      CLKINSTOPPED => open,
      CLKOUT0      => pllout_clk_dmtd,
      CLKOUT0B     => open,
      CLKOUT1      => open,
      CLKOUT1B     => open,
      CLKOUT2      => open,
      CLKOUT2B     => open,
      CLKOUT3      => open,
      CLKOUT3B     => open,
      CLKOUT4      => open,
      CLKOUT5      => open,
      CLKOUT6      => open,
      DO           => open,
      DRDY         => open,
      LOCKED       => open,
      PSDONE       => open,
      CLKFBIN      => u3_CLKFBOUT,
      CLKIN1       => clk20_vcxo,
      CLKIN2       => '0',
      CLKINSEL     => '1',
      DADDR        => (others => '0'),
      DCLK         => '0',
      DEN          => '0',
      DI           => (others => '0'),
      DWE          => '0',
      PSCLK        => '0',
      PSEN         => '0',
      PSINCDEC     => '0',
      PWRDWN       => '0',
      RST          => '0');

  U_WR_CORE: xwr_core
    generic map(
      g_simulation                => g_simulation,
      g_phys_uart                 => true,
      g_virtual_uart              => true,
      g_with_external_clock_input => true,
      g_aux_clks                  => 1,
      g_ep_rxbuf_size             => 1024,
      g_tx_runt_padding           => true,
      g_dpram_initf               => g_dpram_initf,
      g_dpram_size                => g_dpram_size,
      g_interface_mode            => PIPELINED,
      g_address_granularity       => BYTE,
      g_aux_sdb                   => c_wrc_periph3_sdb,
      g_softpll_enable_debugger   => false,
      g_vuart_fifo_size           => 1024,
      g_pcs_16bit                 => true,
      g_records_for_phy           => false,
      g_diag_id                   => 0,
      g_diag_ver                  => 0,
      g_diag_ro_size              => 0,
      g_diag_rw_size              => 0)
    port map(
      clk_sys_i            => clk_sys_i,
      clk_dmtd_i           => clk_dmtd,
      clk_ref_i            => ref_clk_o_net,
      clk_aux_i            => (others => '0'),
      clk_ext_mul_i        => clk_ext_mul_i,
      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
      clk_ext_stopped_i    => '0',
      clk_ext_rst_o        => open,
      clk_ext_i            => clk_ext_i,
      pps_ext_i            => pps_ext_i,
      rst_n_i              => local_reset_n,
      dac_hpll_load_p1_o   => dac_hpll_load_p1_o,
      dac_hpll_data_o      => dac_hpll_data_o,
      dac_dpll_load_p1_o   => dac_dpll_load_p1_o,
      dac_dpll_data_o      => dac_dpll_data_o,
      phy_ref_clk_i        => ref_clk_o_net,
      phy_tx_data_o        => phy_tx_data_o,
      phy_tx_k_o           => phy_tx_k_o,
      phy_tx_disparity_i   => ch1_tx_disparity_o,
      phy_tx_enc_err_i     => ch1_tx_enc_err_o,
      phy_rx_data_i        => rx_data_o,
      phy_rx_rbclk_i       => rx_rbclk_o_net,
      phy_rx_k_i           => rx_k_o,
      phy_rx_enc_err_i     => ch1_rx_enc_err_o,
      phy_rx_bitslide_i    => bitslide_net,
      phy_rst_o            => phy_rst_o,
      phy_rdy_i            => rdy_o,
      phy_loopen_o         => open,
      phy_loopen_vec_o     => phy_loopen_o,
      phy_tx_prbs_sel_o    => tx_prbs_sel,
      phy_sfp_tx_fault_i   => sfp_tx_fault_i,
      phy_sfp_los_i        => sfp_los_i,
      phy_sfp_tx_disable_o => sfp_tx_disable_o,
      phy8_o               => open,
      phy8_i               => open,
      phy16_o              => open,
      phy16_i              => open,
      led_act_o            => LED_ACT,
      led_link_o           => LED_LINK,
      scl_o                => wrc_scl_o,
      scl_i                => wrc_scl_i,
      sda_o                => wrc_sda_o,
      sda_i                => wrc_sda_i,
      sfp_scl_o            => sfp_scl_o,
      sfp_scl_i            => sfp_scl_i,
      sfp_sda_o            => sfp_sda_o,
      sfp_sda_i            => sfp_sda_i,
      sfp_det_i            => sfp_mod_def0_b,
      btn1_i               => button1_i,
      btn2_i               => button2_i,
      spi_sclk_o           => open,
      spi_ncs_o            => open,
      spi_mosi_o           => open,
      spi_miso_i           => '0',
      uart_rxd_i           => uart_rxd_i,
      uart_txd_o           => uart_txd_o,
      owr_pwren_o          => open,
      owr_en_o             => owr_en,
      owr_i                => owr_i,
      slave_i              => wb_bridge_slave_i,
      slave_o              => wb_bridge_slave_o,
      aux_master_o         => wb_bridge_master_o,
      aux_master_i         => wb_bridge_master_i,
      wrf_src_o            => wrf_src_o,
      wrf_src_i            => wrf_src_i,
      wrf_snk_o            => wrf_snk_o,
      wrf_snk_i            => wrf_snk_i,
      timestamps_o         => open,
      timestamps_ack_i     => '1',
      txts_o               => txts_o,
      rxts_o               => rxts_o,
      fc_tx_pause_req_i    => fc_pause_p_i,
      fc_tx_pause_delay_i  => fc_pause_delay_i,
      fc_tx_pause_ready_o  => fc_pause_ack_o,
      tm_link_up_o         => open,
      tm_dac_value_o       => open,
      tm_dac_wr_o          => open,
      tm_clk_aux_lock_en_i => (others => '0'),
      tm_clk_aux_locked_o  => open,
      tm_time_valid_o      => tm_time_valid_o,
      tm_tai_o             => tm_tai_o,
      tm_cycles_o          => tm_cycles_o,
      pps_p_o              => pps_o,
      pps_led_o            => pps_led,
      rst_aux_n_o          => open,
      link_ok_o            => open,
      aux_diag_i           => (others => (others => '0')),
      aux_diag_o           => open);

  U_GTX: wr_gtx_phy_family7
    generic map(
      g_simulation => g_simulation)
    port map(
      clk_gtx_i      => clk_gtx_i,
      tx_out_clk_o   => ref_clk_o_net,
      tx_locked_o    => ref_clk_locked_o,
      tx_data_i      => phy_tx_data_o,
      tx_k_i         => phy_tx_k_o,
      tx_disparity_o => ch1_tx_disparity_o,
      tx_enc_err_o   => ch1_tx_enc_err_o,
      rx_rbclk_o     => rx_rbclk_o_net,
      rx_data_o      => rx_data_o,
      rx_k_o         => rx_k_o,
      rx_enc_err_o   => ch1_rx_enc_err_o,
      rx_bitslide_o  => bitslide_net,
      rst_i          => phy_rst_o,
      loopen_i       => phy_loopen_o,
      tx_prbs_sel_i  => tx_prbs_sel,
      pad_txn_o      => sfp_txn_o,
      pad_txp_o      => sfp_txp_o,
      pad_rxn_i      => sfp_rxn_i,
      pad_rxp_i      => sfp_rxp_i,
      rdy_o          => rdy_o);

    fpga_scl_b <= '0' when wrc_scl_o = '0' else 'Z';
    fpga_sda_b <= '0' when wrc_sda_o = '0' else 'Z';
    wrc_scl_i  <= fpga_scl_b;
    wrc_sda_i  <= fpga_sda_b;


    sfp_mod_def1_b <= '0' when sfp_scl_o = '0' else 'Z';
    sfp_mod_def2_b <= '0' when sfp_sda_o = '0' else 'Z';
    sfp_scl_i      <= sfp_mod_def1_b;
    sfp_sda_i      <= sfp_mod_def2_b;


    thermo_id <= '0' when owr_en(0) = '1' else 'Z';
    owr_i(0)  <= thermo_id;

    dio_onewire_b <= '0' when owr_en(1) = '1' else 'Z';
    owr_i(1)      <= dio_onewire_b;

  --  local_reset_n <= '1';--BUTTON1_I;

  n0: process (clk_sys_i, button1_i) is		-- EASE/HDL sens.list
  begin
  if(rising_edge(clk_sys_i)) then 

          local_reset_n_d0 <= not  button1_i;
          local_reset_n_d1 <=  local_reset_n_d0;
          local_reset_n <=  local_reset_n_d1;
  end if;

  end process n0 ;
end architecture structure ; -- of clb_wrpc

