#!/usr/bin/python

"""
Convert_ShoppingList_to_do_input_file_list.py: Converts
"hdlmake list-files > shoppinglist" file into do_input_file_list.cmd

-------------------------------------------------------------------------------
Copyright (C) 2017 Peter Jansweijer

This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program.  If not, see <http://www.gnu.org/licenses/>
-------------------------------------------------------------------------------

Usage:
  Convert_ShoppingList_to_do_input_file_list.py
  Convert_ShoppingList_to_do_input_file_list.py     -h | --help

  <name>     name of the hdlmake output file that lists al files needed
             in the project (the shopplinlist)
  -o <name>  optional output file name, default: "do_input_file_list.cmd"

Options:
  -h --help    Show this screen.

"""

import os
import sys
import datetime

import pdb

############################################################################

def add_verilog(cmd_file, line):
  cmd_file.write("@echo verilog work " + line + "\" >> %PrjFile%\n")
  cmd_file.write("@echo     ^<file xil_pn:name=" + line + "\" xil_pn:type=\"FILE_VERILOG\"^> >> %XISEFile%\n")
  cmd_file.write("@echo       ^<association xil_pn:name=\"BehavioralSimulation\"/^> >> %XISEFile%\n")
  cmd_file.write("@echo       ^<association xil_pn:name=\"Implementation\"/^> >> %XISEFile%\n")
  cmd_file.write("@echo     ^</file^> >> %XISEFile%\n")
  return()

def add_vhdl(cmd_file, line):
  cmd_file.write("@echo vhdl work " + line + "\" >> %PrjFile%\n")
  cmd_file.write("@echo     ^<file xil_pn:name=" + line + "\" xil_pn:type=\"FILE_VHDL\"^> >> %XISEFile%\n")
  cmd_file.write("@echo       ^<association xil_pn:name=\"BehavioralSimulation\"/^> >> %XISEFile%\n")
  cmd_file.write("@echo       ^<association xil_pn:name=\"Implementation\"/^> >> %XISEFile%\n")
  cmd_file.write("@echo     ^</file^> >> %XISEFile%\n")
  return()


############################################################################
#
# If run from commandline, we can test the library
#
"""
Usage:
  Convert_ShoppingList_to_do_input_file_list.py
  Convert_ShoppingList_to_do_input_file_list.py     -h | --help

  <name>     name of the hdlmake output file that lists al files needed
             in the project (the shopplinlist)
  -o <name>  optional output file name, default: "do_input_file_list.cmd"
  
Options:
  -h --help    Show this screen.

"""
if __name__ == "__main__":

  import argparse
  parser = argparse.ArgumentParser()
  parser.add_argument("name", help="shopping list")
  parser.add_argument("-oname", default="do_input_file_list.cmd", help="outfut file name ")
  args = parser.parse_args()

  name = args.name
  oname = args.oname
  
  if os.path.isfile(name) == True:
    hdlmakelist = open(name,"r")
    if os.path.isfile(oname) == True:
      os.remove(oname)

    xlx_cmd_file = open(oname,"w")
    timestamp = datetime.datetime.now()  #micro secounds timing
    xlx_cmd_file.write("rem do_input_file_list.cmd  PeterJ " + timestamp.strftime("%d %b %Y") + ", AutoGenerated by Convert_ShoppingList_to_do_input_file_list.py \n")
    xlx_cmd_file.write("rem Prepares a .prj file for input to XST\n")
    xlx_cmd_file.write("@prompt $$$s\n")
    xlx_cmd_file.write("\n")
    xlx_cmd_file.write("set lst_LM32_Sources=%1%\n")
    xlx_cmd_file.write("set lst_WRPC_Sources=%2%\n")
    xlx_cmd_file.write("set lst_Arch1Path=%3%\n")
    xlx_cmd_file.write("set PrjFile=%4%.prj\n")
    xlx_cmd_file.write("rem Output to XISEFile can be used to copy/paste into the \".xise\" file of a Xilinx ISE project in order to\n")
    xlx_cmd_file.write("rem run the Xilinx GUI .\n")
    xlx_cmd_file.write("set XISEFile=%4%.ise\n")
    xlx_cmd_file.write("set lst_currentdate=%5%\n")
    xlx_cmd_file.write("set lst_currentrevision=%6%\n")
    xlx_cmd_file.write("set lst_lm32wrpc_dpramsize=%7%\n")
    xlx_cmd_file.write("rem set lst_lm32_2nd_dpramsize=%8%\n")
    xlx_cmd_file.write("rem set lst_clbv2_1=%9%\n")
    xlx_cmd_file.write("\n")
    xlx_cmd_file.write("del %PrjFile%\n")   # restart writing PrjFile and 
    xlx_cmd_file.write("del %XISEFile%\n")  # XISEFile (note '>' not '>>')
    xlx_cmd_file.write("\n")
    
    for line in hdlmakelist:
      line = line.strip()
      if line == "" or line[0] == "#":
        pass
      elif line[-2:] == ".v":
        #add_verilog(xlx_cmd_file, "\"%lst_WRPC_Sources%\\" + line.replace("/","\\"))
        add_verilog(xlx_cmd_file, "\"%lst_WRPC_Sources%/" + line)
      elif line[-4:] == ".vhd":
        #add_vhdl(xlx_cmd_file, "\"%lst_WRPC_Sources%\\" + line.replace("/","\\"))
        add_vhdl(xlx_cmd_file, "\"%lst_WRPC_Sources%/" + line)
        
    hdlmakelist.close()

    """
    
    add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\clb_wrpc\\top\\clb_wrpc.vhd")

    # General and Generic files CLB Related
    add_vhdl(xlx_cmd_file, "..\\..\\general_packages\\V_ARRAY_package.vhd")
    add_vhdl(xlx_cmd_file, "..\\..\\general_packages\\EMAC16bit_package.vhd")
    add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummyMaster.vhd")
    add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummySlave.vhd")
    add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummySink.vhd")
    add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\wb_dummys\\wb_DummySource.vhd")
    add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\stimuli\\ClkRstGen.vhd")
    add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\stimuli\\TransmitFrame16bit.vhd")
    add_vhdl(xlx_cmd_file, "..\\..\\general_modules\\metastabilizer.vhd")

    # IPMUX related
    add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\ipmux\\modules\\clkdist.vhd")
    add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\ipmux\\modules\\reg1en.vhd")
    add_vhdl(xlx_cmd_file, "..\\..\\ip_cores\\ipmux\\top\\ipmux.vhd")
    
    """

    add_vhdl(xlx_cmd_file, "\"../../../ip_cores/clb_wrpc/top/clb_wrpc.vhd")

    # General and Generic files CLB Related
    add_vhdl(xlx_cmd_file, "\"../../../general_packages/V_ARRAY_package.vhd")
    add_vhdl(xlx_cmd_file, "\"../../../general_packages/EMAC16bit_package.vhd")
    add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummyMaster.vhd")
    add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummySlave.vhd")
    add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummySink.vhd")
    add_vhdl(xlx_cmd_file, "\"../../../general_modules/wb_dummys/wb_DummySource.vhd")
    add_vhdl(xlx_cmd_file, "\"../../../general_modules/stimuli/ClkRstGen.vhd")
    add_vhdl(xlx_cmd_file, "\"../../../general_modules/stimuli/TransmitFrame16bit.vhd")
    add_vhdl(xlx_cmd_file, "\"../../../general_modules/metastabilizer.vhd")

    # IPMUX related
    add_vhdl(xlx_cmd_file, "\"../../../ip_cores/ipmux/modules/clkdist.vhd")
    add_vhdl(xlx_cmd_file, "\"../../../ip_cores/ipmux/modules/reg1en.vhd")
    add_vhdl(xlx_cmd_file, "\"../../../ip_cores/ipmux/top/ipmux.vhd")

    # rem General files
    add_vhdl(xlx_cmd_file, "\"%lst_WRPC_Sources%/top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_62_5m.vhd")

    # rem CLB Top Level for FPGA
    add_vhdl(xlx_cmd_file, "\"../../top/fpga.vhd")

    xlx_cmd_file.write("@echo     ^<file xil_pn:name=\"./fpga.ucf\" xil_pn:type=\"FILE_UCF\"^> >> %XISEFile%\n")
    xlx_cmd_file.write("@echo     ^<association xil_pn:name=\"Implementation\"/^> >> %XISEFile%\n")
    xlx_cmd_file.write("@echo     ^</file^> >> %XISEFile%\n")

    # @echo     ^<property xil_pn:name=\"Generics, Parameters\" xil_pn:value=\"g_date_id=%lst_currentdate% g_revision_id=%lst_currentrevision% g_lm32_wrpc_dpram_size=%lst_lm32wrpc_dpramsize% g_lm32_wrpc_profile=%lst_lm32wrpc_profile% g_lm32_2nd_dpram_size=%lst_lm32_2nd_dpramsize% g_lm32_2nd_profile=%lst_lm32_2nd_profile% g_use_clbv2_1=%lst_clbv2_1%" xil_pn:valueState="non-default"/^> >> %XISEFile%
    xlx_cmd_file.write("@echo     ^<property xil_pn:name=\"Generics, Parameters\" xil_pn:value=\"g_date_id=%lst_currentdate% g_revision_id=%lst_currentrevision% g_lm32_wrpc_dpram_size=%lst_lm32wrpc_dpramsize%\" xil_pn:valueState=\"non-default\"/^> >> %XISEFile%\n")
    xlx_cmd_file.write("@echo     ^<property xil_pn:name=\"Other Ngdbuild Command Line Options\" xil_pn:value=\"-bm fpga.bmm -sd %lst_Arch1Path%\" xil_pn:valueState=\"non-default\"/^> >> %XISEFile%\n")
    xlx_cmd_file.write("@echo     ^<property xil_pn:name=\"Other Bitgen Command Line Options\" xil_pn:value=\"-g UnconstrainedPins:Allow\" xil_pn:valueState=\"non-default\"/^> >> %XISEFile%\n")

    xlx_cmd_file.close()
    

sys.exit()
