rem do_input_file_list.cmd  PeterJ 23 Mar 2017, AutoGenerated by Convert_ShoppingList_to_do_input_file_list.py 
rem Prepares a .prj file for input to XST
@prompt $$$s

set lst_LM32_Sources=%1%
set lst_WRPC_Sources=%2%
set lst_Arch1Path=%3%
set PrjFile=%4%.prj
rem Output to XISEFile can be used to copy/paste into the ".xise" file of a Xilinx ISE project in order to
rem run the Xilinx GUI .
set XISEFile=%4%.ise
set lst_currentdate=%5%
set lst_currentrevision=%6%
set lst_lm32wrpc_dpramsize=%7%
rem set lst_lm32_2nd_dpramsize=%8%
rem set lst_clbv2_1=%9%

del %PrjFile%
del %XISEFile%

@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_reset.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_sync_register.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/matrix_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/matrix_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/fabric/xwrf_loopback/lbk_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/fabric/xwrf_loopback/lbk_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/timing/pulse_gen.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/timing/pulse_stamper.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_dacs/spec_serial_dac.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_crc32_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_registers_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_pps_gen/pps_gen_wb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_softpll_ng/softpll_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/gc_escape_detector.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/gc_escape_detector.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/gc_escape_inserter.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/gc_escape_inserter.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/wr_transmission_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_tbi_phy/dec_8b10b.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_tbi_phy/disparity_gen_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_tbi_phy/enc_8b10b.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wrc_core/wb_reset.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wrc_core/wrc_syscon_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/platform/xilinx/wr_gtp_phy/family7-gtx/whiterabbit_gtxe2_channel_wrapper_gt.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_word_packer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gencores_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_dacs/spec_serial_dac_arb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_wishbone_controller.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_si57x_interface/si570_if_wb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/dropping_buffer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/dropping_buffer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/wr_transmission_wb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/wr_transmission_wb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wrc_core/wrc_syscon_wb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_big_adder.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_moving_average.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/fabric/wr_fabric_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/timing/hpll_period_detect.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/timing/multi_dmtd_with_deglitcher.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_auto_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_auto_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_internals_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_internals_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_queue_auto_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_queue_auto_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_tlu_auto_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_tlu_auto_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_mini_nic/minic_wb_slave.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_si57x_interface/wr_si57x_interface.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_si57x_interface/wr_si57x_interface.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_tbi_phy/wr_tbi_phy.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_tlu/tlu_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_tlu/tlu_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/platform/xilinx/wr_gtp_phy/family7-gtx/wr_gtx_phy_family7.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/fabric/xwb_fabric_sink.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/fabric/xwb_fabric_source.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/fabric/xwrf_mux.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/fabric/xwrf_reg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/fabric/xwrf_reg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/timing/dmtd_with_deglitcher.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_ac_wbm_auto.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_ac_wbm_auto.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_adder.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_auto.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_auto.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_offset.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_queue_auto.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_queue_auto.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_sdp.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_tdp.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_tdp.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_tlu_auto.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_tlu_auto.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_tlu_fsm.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_tlu_fsm.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/endpoint_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_bypass_queue.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_pps_gen/wr_pps_gen.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_si57x_interface/xwr_si57x_interface.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_softpll_ng/spll_aligner.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_softpll_ng/spll_aligner.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_softpll_ng/spll_period_detect.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_tlu/tlu_fsm.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wrc_core/xwr_syscon_wb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/timing/dmtd_phase_meas.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_data.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_data.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_free.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_free.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_msi.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_msi.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_piso_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_piso_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_queue.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_queue.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_rmw.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_rmw.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_scan.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_scan.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_scubus_channel.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_scubus_channel.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_search.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_tlu.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_tlu.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_walker.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_wb_event.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_wr_time.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/endpoint_private_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_mini_nic/minic_packet_buffer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_mini_nic/minic_packet_buffer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_pps_gen/xwr_pps_gen.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/xrx_streamer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_tlu/tlu.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_tlu/tlu.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wrc_core/wrc_dpram.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wrc_core/wrcore_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/platform/xilinx/wr_xilinx_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/board/common/wr_board_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/board/common/wr_board_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_tag_channel.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_tag_channel.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_autonegotiation.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_leds_controller.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_packet_filter.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rtu_header_extract.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_crc_size_check.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_early_address_match.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_oob_insert.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_vlan_unit.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_wb_master.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_sync_detect.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_sync_detect_16bit.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_ts_counter.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_crc_inserter.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_header_processor.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_packet_injection.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_packet_injection.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_vlan_unit.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_vlan_unit.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/rx_streamer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/rx_streamer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/streamers_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/streamers_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/platform/xilinx/xwrc_platform_xilinx.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/platform/xilinx/xwrc_platform_xilinx.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/board/spec/wr_spec_pkg.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/board/spec/wr_spec_pkg.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo verilog work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_ac_wbm.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_ac_wbm.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca_channel.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_buffer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_timestamping_unit.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_path.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_mini_nic/wr_mini_nic.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/xrtx_streamers_stats.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/xrtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/xtx_streamer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/xtx_streamer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/fabric/xwrf_loopback/wrf_loopback.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/fabric/xwrf_loopback/wrf_loopback.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/eca.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_1000basex_pcs.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_path.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_mini_nic/xwr_mini_nic.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_softpll_ng/spll_wb_slave.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/tx_streamer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/tx_streamer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_streamers/xwr_transmission.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_streamers/xwr_transmission.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_eca/wr_eca.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/wr_endpoint.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_softpll_ng/wr_softpll_ng.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wrc_core/wrc_periph.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_endpoint/xwr_endpoint.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wr_softpll_ng/xwr_softpll_ng.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wrc_core/wr_core.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/modules/wrc_core/xwr_core.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../ip_cores/clb_wrpc/top/clb_wrpc.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../ip_cores/clb_wrpc/top/clb_wrpc.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../general_packages/V_ARRAY_package.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../general_packages/V_ARRAY_package.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../general_packages/EMAC16bit_package.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../general_packages/EMAC16bit_package.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../general_modules/wb_dummys/wb_DummyMaster.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../general_modules/wb_dummys/wb_DummyMaster.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../general_modules/wb_dummys/wb_DummySlave.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../general_modules/wb_dummys/wb_DummySlave.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../general_modules/wb_dummys/wb_DummySink.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../general_modules/wb_dummys/wb_DummySink.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../general_modules/wb_dummys/wb_DummySource.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../general_modules/wb_dummys/wb_DummySource.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../general_modules/stimuli/ClkRstGen.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../general_modules/stimuli/ClkRstGen.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../general_modules/stimuli/TransmitFrame16bit.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../general_modules/stimuli/TransmitFrame16bit.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../general_modules/metastabilizer.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../general_modules/metastabilizer.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../ip_cores/ipmux/modules/clkdist.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../ip_cores/ipmux/modules/clkdist.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../ip_cores/ipmux/modules/reg1en.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../ip_cores/ipmux/modules/reg1en.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../../ip_cores/ipmux/top/ipmux.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../../ip_cores/ipmux/top/ipmux.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "%lst_WRPC_Sources%/top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_62_5m.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="%lst_WRPC_Sources%/top/kintex7_ref_design/wr_core_demo/ext_pll_10_to_62_5m.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo vhdl work "../../top/fpga.vhd" >> %PrjFile%
@echo     ^<file xil_pn:name="../../top/fpga.vhd" xil_pn:type="FILE_VHDL"^> >> %XISEFile%
@echo       ^<association xil_pn:name="BehavioralSimulation"/^> >> %XISEFile%
@echo       ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo     ^<file xil_pn:name="./fpga.ucf" xil_pn:type="FILE_UCF"^> >> %XISEFile%
@echo     ^<association xil_pn:name="Implementation"/^> >> %XISEFile%
@echo     ^</file^> >> %XISEFile%
@echo     ^<property xil_pn:name="Generics, Parameters" xil_pn:value="g_date_id=%lst_currentdate% g_revision_id=%lst_currentrevision% g_lm32_wrpc_dpram_size=%lst_lm32wrpc_dpramsize%" xil_pn:valueState="non-default"/^> >> %XISEFile%
@echo     ^<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="-bm fpga.bmm -sd %lst_Arch1Path%" xil_pn:valueState="non-default"/^> >> %XISEFile%
@echo     ^<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="-g UnconstrainedPins:Allow" xil_pn:valueState="non-default"/^> >> %XISEFile%
