--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 9 from HDL Works B.V.
--
-- Ease library  : work
-- HDL library   : work
-- Host name     : SERING
-- User name     : peterj
-- Time stamp    : Thu Oct 17 11:14:21 2013
--
-- Designed by   : 
-- Company       : HDL Works
-- Project info  : 
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Object        : Entity work.MetaStabilizer
-- Last modified : Mon Jan 14 15:05:19 2013.
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity MetaStabilizer is
   generic(
     g_simulation : integer := 0);
   port (
    Clk     : in     std_logic;
    RESET   : in     std_logic;
    EOS     : in     std_logic;
    O       : out    std_logic;
    O_n     : out    std_logic);
end entity MetaStabilizer;

--------------------------------------------------------------------------------
-- Object        : Architecture work.MetaStabilizer.rtl
-- Last modified : Mon Jan 14 15:05:19 2013.
--------------------------------------------------------------------------------

architecture rtl of MetaStabilizer is
   signal tc     : std_logic := '0';
begin
   Process (Clk, EOS)
      Variable Meta_1, Meta_2, TerminalCount: Std_Logic;
      Variable Cnt: Unsigned (9 downto 0);  -- 2^9 = 512 * 16 ns = 8192 ns reset time
   Begin
      If EOS = '0' Then
         Meta_1 := '0';
         Meta_2 := '0';
         TerminalCount := '0';
         Cnt := (others => '0');
         tc <= '0';
      ElsIf Rising_Edge(Clk) Then
         Meta_2 := Meta_1;
         Meta_1 := not RESET;

         If Meta_2 = '1' Then
            If g_simulation = 1 Then
               TerminalCount := Cnt(Cnt'Right);
            Else
               TerminalCount := Cnt(Cnt'Left);
            End If;
            
            If TerminalCount = '1' Then
               tc <= '1';
            Else
               Cnt := Cnt + 1;
               tc <= '0';
            End If;
         Else
            Cnt := (Others => '0');
            tc <= '0';
         End If;
      End If;
   End Process;

   O <= not tc;
   O_n <= tc;

end architecture rtl ; -- of MetaStabilizer

