--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 7.4 Revision 9 from HDL Works B.V.
--
-- Ease library  : work
-- HDL library   : work
-- Host name     : SERING
-- User name     : peterj
-- Time stamp    : Mon Aug 12 13:45:21 2013
--
-- Designed by   : 
-- Company       : 
-- Project info  : 
--
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
-- Object        : Entity work.ClkRstGen
-- Last modified : Wed Jul 24 11:58:09 2013.
--------------------------------------------------------------------------------

library ieee, work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ClkRstGen is
  port(
    clk_20m_vcxo : out    std_logic;
    MGTCLK_N     : out    std_logic;
    MGTCLK_P     : out    std_logic;
    RESET        : out    std_logic;
    SysClk_n     : out    std_logic;
    SysClk_p     : out    std_logic);
end entity ClkRstGen;

--------------------------------------------------------------------------------
-- Object        : Architecture work.ClkRstGen.rtl
-- Last modified : Wed Jul 24 11:58:09 2013.
--------------------------------------------------------------------------------


architecture rtl of ClkRstGen is
signal int_clk_20m : std_logic := '0';
signal int_clk125p : std_logic := '0';
signal int_clk125n : std_logic := '1';
signal int_clk200p : std_logic := '0';
signal int_clk200n : std_logic := '1';

begin
  int_clk_20m    <= not int_clk_20m after 25 ns;

  int_clk125p    <= not int_clk125p after 4 ns;
  int_clk125n    <= not int_clk125n after 4 ns;

  int_clk200p    <= not int_clk200p after 2500 ps;
  int_clk200n    <= not int_clk200n after 2500 ps;

  clk_20m_vcxo <= int_clk_20m;

  MGTCLK_P <= int_clk125p;
  MGTCLK_N <= int_clk125n;

  SysClk_p <= int_clk200p;
  SysClk_n <= int_clk200n;

  reset <= '1', '0' after 1000 ns; 

end architecture rtl ; -- of ClkRstGen

